JP7298195B2 - 光モジュール及びその製造方法 - Google Patents

光モジュール及びその製造方法 Download PDF

Info

Publication number
JP7298195B2
JP7298195B2 JP2019039752A JP2019039752A JP7298195B2 JP 7298195 B2 JP7298195 B2 JP 7298195B2 JP 2019039752 A JP2019039752 A JP 2019039752A JP 2019039752 A JP2019039752 A JP 2019039752A JP 7298195 B2 JP7298195 B2 JP 7298195B2
Authority
JP
Japan
Prior art keywords
electrode pads
conductive material
conductive
semiconductor chip
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019039752A
Other languages
English (en)
Other versions
JP2020144192A (ja
Inventor
健人 高橋
輝洋 久保
弘 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Optical Components Ltd
Original Assignee
Fujitsu Optical Components Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Optical Components Ltd filed Critical Fujitsu Optical Components Ltd
Priority to JP2019039752A priority Critical patent/JP7298195B2/ja
Priority to US16/806,256 priority patent/US11495589B2/en
Publication of JP2020144192A publication Critical patent/JP2020144192A/ja
Application granted granted Critical
Publication of JP7298195B2 publication Critical patent/JP7298195B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12004Combinations of two or more optical elements
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H01P11/001Manufacturing waveguides or transmission lines of the waveguide type
    • H01P11/003Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/003Coplanar lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6638Differential pair signal lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/1319Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13561On the entire surface of the core, i.e. integral coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405Shape
    • H01L2224/14051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1415Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/14179Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145Material
    • H01L2224/14505Bump connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751Function
    • H01L2224/17515Bump connectors having different functions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/278Post-treatment of the layer connector
    • H01L2224/27848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/27849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29012Shape in top view
    • H01L2224/29013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/29294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301Disposition
    • H01L2224/3012Layout
    • H01L2224/3015Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32052Shape in top view
    • H01L2224/32053Shape in top view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32052Shape in top view
    • H01L2224/32054Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32052Shape in top view
    • H01L2224/32056Shape in top view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3305Shape
    • H01L2224/33051Layer connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • H01L2224/33505Layer connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499Material of the matrix
    • H01L2224/81594Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/815 - H01L2224/81591
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/83498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83499Material of the matrix
    • H01L2224/83594Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/835 - H01L2224/83591
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/83498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83598Fillers
    • H01L2224/83599Base material
    • H01L2224/836Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/142HF devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/381Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Light Receiving Elements (AREA)

Description

本発明は、光モジュール及びその製造方法に関する。
コヒーレント用光通信用の光半導体チップには、小型化及び多ピン化が要望されている。そこで、ボールグリッドアレイ(ball grid array:BGA)パッケージの光半導体チップが光モジュールに用いられることがある。
しかしながら、従来のBGAパッケージの光半導体チップを用いた光モジュールでは、優れた高周波特性を確保しながら微細化することが困難である。
特開平9-64238号公報 特開2000-269384号公報 米国特許第9607863号明細書
本開示の目的は、優れた高周波特性を確保しながら微細化することができる光モジュール及びその製造方法を提供することにある。
本開示の一形態によれば、複数の第1の電極パッドと、複数の第2の電極パッドと、前記複数の第1の電極パッドと前記複数の第2の電極パッドとの間に配置された複数の第3の電極パッドと、を備えた光半導体チップと、複数の第4の電極パッドと、複数の第5の電極パッドと、前記複数の第4の電極パッドと前記複数の第5の電極パッドとの間に配置された複数の第6の電極パッドと、備え、前記光半導体チップがフリップチップ実装された配線基板と、それぞれ、前記複数の第1の電極パッドのうちの一つと前記複数の第4の電極パッドのうちの一つとを接続する複数の第1の導電材と、それぞれ、前記複数の第2の電極パッドのうちの一つと前記複数の第5の電極パッドのうちの一つとを接続する複数の第2の導電材と、前記複数の第1の導電材と前記複数の第2の導電材との間に配置された1又は2以上の第3の導電材と、前記光半導体チップと前記配線基板との間で、前記第3の導電材の前記第2の導電材側に設けられた樹脂と、を有し、前記第2の導電材は前記樹脂に接触し、前記第1の導電材は前記樹脂に非接触であり、前記光半導体チップは、前記第3の導電材の前記第1の導電材側に設けられた複数の第7の電極パッドを有し、前記配線基板は、前記第3の導電材の前記第1の導電材側に設けられた複数の第8の電極パッドを有し、前記第3の導電材の前記第1の導電材側に設けられ、それぞれ、前記複数の第7の電極パッドのうちの一つと前記複数の第8の電極パッドのうちの一つとを接続する複数の第4の導電材を有し、前記1又は2以上の第3の導電材の各々は、前記複数の第3の電極パッドと前記複数の第6の電極パッドとを接続し、前記第1の導電材を介して伝送される信号の第1の速度が、前記第2の導電材を介して伝送される信号の第2の速度よりも速く、前記複数の第1の導電材、前記複数の第2の導電材及び前記第4の導電材のうちの同一直線上にない少なくとも3個で、すべてではない導電材はコア材を有し、前記コア材の融点は半田の融点よりも高い光モジュールが提供される。
本開示によれば、優れた高周波特性を確保しながら微細化することができる。
第1の実施形態に係る光モジュールの構成を示すブロック図である。 第1の実施形態に係る光モジュールに含まれる光半導体チップの構造を示す下面図である。 第1の実施形態に係る光モジュールの構造を示す平面図である。 第1の実施形態に係る光モジュールの構造を示す断面図である。 第1の実施形態における、配線基板、導電材及びアンダーフィルの関係を示す図である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その1)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その2)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その3)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その4)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その5)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その6)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その7)である。 第1の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その8)である。 第2の実施形態に係る光モジュールの構造を示す断面図である。 第2の実施形態における、配線基板、導電材及びアンダーフィルの関係を示す図である。 第2の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その1)である。 第2の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その2)である。 第2の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その3)である。 第2の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その4)である。 第2の実施形態に係る光モジュールの製造方法における、光半導体チップを配線基板に実装する方法を示す断面図(その5)である。 第2の実施形態の変形例における、配線基板、導電材及びアンダーフィルの関係を示す図である。 第1の実施形態の第1の変形例における、配線基板、導電材及びアンダーフィルの関係を示す図である。 第1の実施形態の第2の変形例における、配線基板、導電材及びアンダーフィルの関係を示す図である。 第1の実施形態の第3の変形例における、光半導体チップの構造を示す下面図である。 第1の実施形態の第3の変形例に係る光モジュールの構造を示す平面図である。
本願発明者らは、優れた高周波特性を確保しながら更に微細化することが困難な理由を明らかにすべく鋭意検討を行った。
光半導体チップの微細化のために、BGAの半田ボールのピッチは狭められ、直径が小さくされる。直径が小さくなるほど、半田ボールにクラックが生じる応力が小さくなり、接続信頼性が低下しやすくなる。接続信頼性の低下を抑制するためには、光半導体チップと配線基板との間の空間に、アンダーフィルとよばれる液状の樹脂を流し込み、硬化させることが有効である。しかしながら、光半導体チップと配線基板との間の空間がアンダーフィルで充填されると、樹脂の誘電率の影響により、高速信号が伝送される半田ボールに特性インピーダンスの不整合が生じる。この結果、高周波特性が低下してしまう。
以下、実施形態について添付の図面を参照しながら具体的に説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複した説明を省くことがある。また、本開示においては、X1-X2方向、Y1-Y2方向、Z1-Z2方向を相互に直交する方向とする。また、X1-X2方向及びY1-Y2方向を含む面をXY面と記載し、Y1-Y2方向及びZ1-Z2方向を含む面をYZ面と記載し、Z1-Z2方向及びX1-X2方向を含む面をZX面と記載する。なお、便宜上、Z1-Z2方向を上下方向とする。また、平面視とは、Z1側から対象物を見ることをいう。
(第1の実施形態)
まず、第1の実施形態について説明する。図1は、第1の実施形態に係る光モジュールの構成を示すブロック図である。図1中の実線の矢印は電気信号が伝送される方向を示し、破線は光信号が伝送される方向を示す。
第1の実施形態に係る光モジュール1は、光半導体チップ200と、デジタルシグナルプロセッサ(digital signal processor:DSP)300と、レーザ400とを含む。光半導体チップ200は、集積コヒーレントレシーバ(integrated coherent receiver:ICR)210と、ドライバ220と、変調器I230とを含む。
ICR210は、光ファイバ500(図3参照)を通じて光モジュール1に外部から出射された信号光(Rx Opt)とレーザ400が発した局発光とを入力し、電気信号を出力する。DSP300は、ICR210が出力した電気信号を入力し、これを処理してデータ信号(Rx Data)を外部に出力する。DSP300は、外部からデータ信号(Tx Data)を入力し、これを処理してドライバ220に出力する。ドライバ220は、DSP300が出力した信号に基づいて変調器230を駆動する。変調器230は、ドライバ220により駆動さ、レーザ400が発した局発光を変調して信号光(Tx Opt)を、光ファイバ500を通して光モジュール1の外部に出射する。
図2は、光半導体チップ200の構造を示す下面図である。光半導体チップ200はボールグリッドアレイ(ball grid array:BGA)パッケージを有する。図2に示すように、光半導体チップ200の下面に複数の電極パッド240が設けられている。電極パッド240は格子状に配置されている。複数の電極パッド240の一部は高速信号用の電極パッド240Hであり、他の一部は接地用の電極パッド240Gであり、他の一部は低速信号用の電極パッド240Lである。例えば、光半導体チップ200の平面形状は長方形であり、電極パッド240Hは、平面視で、DSP300側(X1側)に配置される辺の近傍に集中して配置されている。例えば、隣り合う2個の電極パッド240Hを通じて差動信号が伝送され、差動信号が伝送される2個の電極パッド240Hを挟むように2個の電極パッド240Gが配置されている。また、電極パッド240が最近接で並ぶ方向において、電極パッド240Hと電極パッド240Lとの間には、電極パッド240Gが配置されている。電極パッド240Hは第1の電極パッドの一例であり、電極パッド240Lは第2の電極パッドの一例であり、電極パッド240Hと電極パッド240Lとの間に配置された電極パッド240Gは、第3の電極パッドの一例である。
図3Aは、第1の実施形態に係る光モジュール1の構造を示す平面図である。図3Bは、第1の実施形態に係る光モジュール1の構造を示す断面図である。図3Bは、図3A中のI-I線に沿った断面図に相当する。
配線基板100の上面に複数の電極パッド120が、平面視で電極パッド240と重なるようにして格子状に配置されている。複数の電極パッド120の一部は電極パッド240Hが電気的に接続される電極パッド120Hであり、他の一部は電極パッド240Gが電気的に接続される電極パッド120Gであり、他の一部は電極パッド240Lが電気的に接続される電極パッド120Lである。電極パッド120Hは第4の電極パッドの一例であり、電極パッド120Lは第5の電極パッドの一例である。複数の電極パッド120Gの一部は、電極パッド120Hと電極パッド120Lとの間に配置され、第6の電極パッドの一例である。
光半導体チップ200は配線基板100にフリップチップ実装されている。1個の電極パッド240Hは、個々に円柱状の1個の導電材620Hを介して1個の電極パッド120Hに電気的、機械的に接続されている。1個の電極パッド240Lは、個々に円柱状の1個の導電材620Lを介して1個の電極パッド120Lに電気的、機械的に接続されている。複数の電極パッド240Gの一部は、個々に円柱状の1個の導電材620Gを介して1個の電極パッド120Gに電気的、機械的に接続されている。複数の電極パッド240Gの残部は、壁状の1個の導電材620GWを介して複数の電極パッド120Gに電気的、機械的に接続されている。導電材620H、導電材620L、導電材620G及び導電材620GWの材料は、例えば半田である。導電材620Hは第1の導電材の一例であり、導電材620Lは第2の導電材の一例であり、導電材620GWは第3の導電材の一例である。
DSP300もBGAパッケージを有しており、配線基板100にフリップチップ実装されている。DSP300の下面に複数の電極パッド340が設けられている。電極パッド340は格子状に配置されている。複数の電極パッド340の一部は高速信号用の電極パッド340Hであり、他の一部は接地用の電極パッド340Gであり、更に他の一部は他の用途に用いられる電極パッド340Aである。例えば、DSP300の平面形状は長方形であり、電極パッド340Hは、平面視で、光半導体チップ200側に配置される辺の近傍に集中して配置されている。例えば、隣り合う2個の電極パッド340Hを通じて差動信号が伝送され、差動信号が伝送される2個の電極パッド340Hを挟むように2個の電極パッド340Gが配置されている。
配線基板100の上面に複数の電極パッド130が、平面視で電極パッド340と重なるようにして格子状に配置されている。複数の電極パッド130の一部は電極パッド340Hが電気的に接続される電極パッド130Hであり、他の一部は電極パッド340Gが電気的に接続される電極パッド130Gであり、他の一部は電極パッド340Aが電気的に接続される電極パッド130Aである。1個の電極パッド340Hは、個々に円柱状の1個の導電材630Hを介して1個の電極パッド130Hに電気的、機械的に接続されている。1個の電極パッド340Gは、個々に円柱状の1個の導電材(図示せず)を介して1個の電極パッド130Gに電気的、機械的に接続されている。1個の電極パッド340Aは、個々に円柱状の1個の導電材630Aを介して1個の電極パッド130Aに電気的、機械的に接続されている。導電材630H、電極パッド340Gと電極パッド130Gとを接続する導電材(図示せず)、及び導電材630Aの材料は、例えば半田である。
配線基板100は、電極パッド120Hと電極パッド130Hとを結ぶ信号線路150Hと、電極パッド120Gと電極パッド130Gとを結ぶ接地線路150Gとを有する。例えば、信号線路150Hは配線基板100の表層部に形成されており、直線状に延びるコプレーナ線路又はマイクロストリップ線路である。例えば、複数の信号線路150Hは等長配線である。また、複数の信号線路150Hは、差動信号が伝送される2本の信号線路を含んでおり、差動信号が伝送される2本の信号線路を間に挟むようにして2本の接地線路150Gが配置されている。つまり、配線基板100は、2本の信号線路150H及び2本の接地線路150Gから構成されたGSSG配線を含む。例えば、信号線路150Hの特性インピーダンスは50Ω程度であり、複数の信号線路150Hの間で特性インピーダンスが整合している。
上記のように、複数の電極パッド240Gが1個の導電材620Gを介して複数の電極パッド120Gに電気的、機械的に接続されている。より具体的には、配線基板100と光半導体チップ200と間の空間が、導電材620Gによって、導電材620Hが設けられた空間と、導電材620Lが設けられた空間とに分離されている。つまり、導電材620Gによって、導電材620Hが設けられた空間と、導電材620Lが設けられた空間とが互いから隔離されている。そして、配線基板100と光半導体チップ200と間の空間のうち、導電材620Lが設けられた空間にアンダーフィル190が充填され、導電材620Hが設けられた空間にはアンダーフィル190が充填されていない。つまり、導電材620Hの周囲にはアンダーフィル190が設けられていない。図3Cに、第1の実施形態における、配線基板100、導電材620H、導電材620G、導電材620GW、導電材620L及びアンダーフィル190の関係を示す。図3C等に示すように、導電材620Lはアンダーフィル190に接触し、導電材620Hはアンダーフィル190に非接触である。アンダーフィル190は樹脂の一例である。
第1の実施形態に係る光モジュール1では、例えば、光半導体チップ200とDSP300との間で、例えば、信号線路150Hを介して周波数が最大30GHz以上の信号が伝送される。つまり、導電材620Hを介して伝送される信号の周波数は最大30GHz以上である。そして、導電材620Hを介して伝送される信号の速度(第1の速度)が、導電材620Lを介して伝送される信号の速度(第2の速度)より速い。また、導電材620G及び導電材620GWは接地される。
光モジュール1によれば、アンダーフィル190が設けられているため、小型化しても優れた強度を得ることができる。また、アンダーフィル190は壁状の導電材620GWの導電材620L側に形成され、導電材620H側には形成されていないため、アンダーフィル190の誘電率に起因する高周波特性の劣化を回避することができる。
また、配線基板100と光半導体チップ200との間の接地線路として用いる導電材620GWにより導電材620L側の空間と導電材620H側の空間とが隔離されるため、隔離のためだけに用いる部材を形成する必要がない。従って、コストの上昇を抑制することができる。
次に、第1の実施形態に係る光モジュール1の製造方法における、光半導体チップ200を配線基板100に実装する方法について説明する。図4A~図4Hは、第1の実施形態に係る光モジュール1の製造方法における、光半導体チップ200を配線基板100に実装する方法を示す断面図である。図4A~図4Hには、図2中のI-I線に沿った断面の変化を示す。
まず、図4Aに示すように、電極パッド240H、電極パッド240G及び電極パッド240Lを含む光半導体チップ200を準備する。次いで、複数の電極パッド240Gのうちの一部の表面上を含む、導電材620GWを形成する予定の領域に半田ペースト620Aを設ける。半田ペースト620Aは、例えばスクリーン印刷により設けることができる。
次いで、リフローを行うことにより、図4Bに示すように、壁状の導電材620Bを形成する。
その後、図4Cに示すように、電極パッド240Hの表面上、電極パッド240Lの表面上、及び残りの電極パッド240G(複数の電極パッド240Gのうちで導電材620Bが設けられていない電極パッド240G)の表面上に半田ボール620Cを載置する。
続いて、リフローを行うことにより、図4Dに示すように、電極パッド240Hの表面上、電極パッド240Lの表面上及び残りの電極パッド240Gの表面上に、個々に導電材620Dを形成する。
また、図4Eに示すように、電極パッド120H、電極パッド120G及び電極パッド120Lを含む配線基板100を準備する。次いで、電極パッド120Hの表面上、電極パッド120Gの表面上及び電極パッド120Lの表面上に半田ペースト629を設ける。半田ペースト629は、例えばスクリーン印刷により設けることができる。図4E~図4Gに図示しないが、配線基板100は、電極パッド130H、電極パッド130G及び電極パッド130Aも含む。
その後、図4Fに示すように、配線基板100上に光半導体チップ200を載置する。このとき、平面視で、電極パッド240Hと電極パッド120Hとが重なり、電極パッド240Gと電極パッド120Gとが重なり、電極パッド240Lと電極パッド120Lとが重なるように位置合わせを行う。
続いて、リフローを行う。この結果、図4Gに示すように、電極パッド240Hと電極パッド120Hとの間では、半田ペースト629と導電材620Dとが一体化して円柱状の導電材620Hが形成される。電極パッド240Lと電極パッド120Lとの間では、半田ペースト629と導電材620Dとが一体化して円柱状の導電材620Lが形成される。複数の電極パッド240Gの一部と電極パッド120Gとの間では、半田ペースト629と導電材620Dとが一体化して円柱状の導電材620G(図3C参照)が形成される。複数の電極パッド240Gの残部と電極パッド120Gとの間では、半田ペースト629と導電材620Bとが一体化して壁状の導電材620GWが形成される。導電材620GWによって、導電材620Hが設けられた空間と、導電材620Lが設けられた空間とが互いから隔離される。
次いで、図4Hに示すように、配線基板100と光半導体チップ200と間の空間のうち、導電材620Lが設けられた空間にアンダーフィル190を充填する。このとき、導電材620GWによって、導電材620Hが設けられた空間と、導電材620Lが設けられた空間とが互いから隔離されているため、導電材620Hが設けられた空間にはアンダーフィル190が充填されない。
このようにして、光半導体チップ200を配線基板100に実装することができる。
更に、DSP300及びレーザ400を配線基板100に実装することで、第1の実施形態に係る光モジュール1を製造することができる。なお、DSP300は光半導体チップ200と並行して配線基板100に実装してもよい。
この製造方法によれば、導電材620GWを形成しておくことにより、高速信号が伝送される導電材620H側へのアンダーフィル190の流れ込みを確実に防止することができる。また、導電材620GWにより導電材620L側の空間と導電材620H側の空間とが隔離されるため、隔離のためだけに用いる部材を形成する必要がない。従って、コストの上昇を抑制することができる。
(第2の実施形態)
次に、第2の実施形態について説明する。第2の実施形態は、光半導体チップ200と配線基板100との間の導電材の構成の点で第1の実施形態と相違する。図5Aは、第2の実施形態に係る光モジュールの構造を示す断面図である。図5Aには、第1の実施形態の図3A中のI-I線に沿った断面に相当する断面のうち、光半導体チップ200が設けられた部分を示す。図5Bは、第2の実施形態における、配線基板、導電材及びアンダーフィルの関係を示す図である。
図5A及び図5Bに示すように、第2の実施形態に係る光モジュール2は、導電材620Hに代えて導電材625Hを有し、導電材620Lに代えて導電材625Lを有し、導電材620Gに代えて導電材625Gを有する。導電材625Hは、いずれも、コア材621Hと、コア材621Hを被覆する導電被覆材622Hとを有する。導電材625Lは、いずれも、コア材621Lと、コア材621Lを被覆する導電被覆材622Lとを有する。導電材625Gは、いずれも、コア材621Gと、コア材621Gを被覆する導電被覆材622Gとを有する。コア材621H、コア材621L及びコア材621Gの材料は、例えば銅(Cu)又は銅合金等の融点が半田の融点よりも高い金属である。コア材621H、コア材621L及びコア材621Gの材料に耐熱性樹脂を用いてもよい。コア材621H、コア材621L及びコア材621Gの直径は、実質的に同一である。
第2の実施形態によっても第1の実施形態と同様の効果を得ることができる。更に、詳細は後述するが、配線基板100と光半導体チップ200との間の距離を安定させ、高周波特性の安定性を向上することができる。
次に、第2の実施形態に係る光モジュール1の製造方法における、光半導体チップ200を配線基板100に実装する方法について説明する。図6A~図6Eは、第2の実施形態に係る光モジュール2の製造方法における、光半導体チップ200を配線基板100に実装する方法を示す断面図である。図6A~図6Eには、図2中のI-I線に沿った断面に相当する断面の変化を示す。
まず、第1の実施形態と同様にして、壁状の導電材620Bを形成する処理まで行う(図4B参照)。次いで、図6Aに示すように、電極パッド240Hの表面上、電極パッド240Lの表面上及び残りの電極パッド240G(複数の電極パッド240Gのうちで導電材620Bが設けられていない電極パッド240G)の表面上に、コア材621と、コア材621を被覆する導電被覆材622とを有する半田ボール625を載置する。
その後、リフローを行うことにより、図6Bに示すように、電極パッド240Hの表面上、電極パッド240Lの表面上及び残りの電極パッド240Gの表面上に、個々に、コア材621を含む導電材625Dを形成する。
続いて、図6Cに示すように、半田ペースト629が設けられた配線基板100上に光半導体チップ200を載置する。このとき、平面視で、電極パッド240Hと電極パッド120Hとが重なり、電極パッド240Gと電極パッド120Gとが重なり、電極パッド240Lと電極パッド120Lとが重なるように位置合わせを行う。
次いで、リフローを行う。この結果、図6Dに示すように、電極パッド240Hと電極パッド120Hとの間では、半田ペースト629と導電材625Dとが一体化して導電材625Hが形成される。電極パッド240Lと電極パッド120Lとの間では、半田ペースト629と導電材625Dとが一体化して導電材625Lが形成される。複数の電極パッド240Gの一部と電極パッド120Gとの間では、半田ペースト629と導電材625Dとが一体化して円柱状の導電材625G(図5B参照)が形成される。複数の電極パッド240Gの残部と電極パッド120Gとの間では、半田ペースト629と導電材620Bとが一体化して壁状の導電材620GWが形成される。導電材620GWによって、導電材625Hが設けられた空間と、導電材625Lが設けられた空間とが互いから隔離される。
その後、図6Eに示すように、配線基板100と光半導体チップ200と間の空間のうち、導電材625Lが設けられた空間にアンダーフィル190を充填する。このとき、導電材620GWによって、導電材625Hが設けられた空間と、導電材625Lが設けられた空間とが互いから隔離されているため、導電材625Hが設けられた空間にはアンダーフィル190が充填されない。
このようにして、光半導体チップ200を配線基板100に実装することができる。
更に、DSP300及びレーザ400を配線基板100に実装することで、第1の実施形態に係る光モジュール1を製造することができる。なお、DSP300は光半導体チップ200と並行して配線基板100に実装してもよい。
第2の実施形態では、導電材625Hがコア材621Hを含み、導電材625Lがコア材621Lを含み、導電材625Gがコア材621Gを含む。従って、配線基板100と光半導体チップ200との間の距離を安定させることができる。すなわち、配線基板100上に光半導体チップ200を載置した後のリフロー(図6D参照)では、溶融した導電材620B及び導電被覆材622が個々に表面張力を発揮する。このとき、導電被覆材622の体積が導電材620Bの体積よりも大きいため、導電被覆材622が導電材620Bよりも配線基板100と光半導体チップ200との間の距離を強く縮小しようとする。このため、第1の実施形態では、配線基板100と光半導体チップ200との間の距離にばらつきが生じることがある。例えば、配線基板100と光半導体チップ200との間の距離がX1側で短く、X側で長くなることがある。これに対し、第2の実施形態では、導電被覆材622が導電材620Bよりも配線基板100と光半導体チップ200との間の距離を強く縮小しようとしても、コア材621H、コア材621L及びコア材621Gが含まれているため、配線基板100と光半導体チップ200との間の距離を安定させることができる。
一般に高速信号が伝送される伝送線路では、特性インピーダンスZを安定させることが重要である。導電材620H及び導電材625Hに着目すると、特性インピーダンスZは、導電材620H及び導電材625Hの高さに関するインダクタンスLと、導電材620H及び導電材625Hと導電材620GWとの間の距離に関するキャパシタンスCとに依存する。特性インピーダンスZは、Z=(L/C)1/2で表すことができる。従って、配線基板100と光半導体チップ200との間の距離を安定できることは、高周波特性の安定性の観点から極めて好ましい。
なお、全ての導電材625Hがコア材621Hを含み、全ての導電材625Lがコア材621Lを含み、全ての導電材625Gがコア材621Gを含む必要はない。例えば、図7に示すように、少なくとも直線上にない3個の導電材620H、導電材620L又は導電材620Gにコア材が含まれていればよい。図7は、第2の実施形態の変形例における、配線基板、導電材及びアンダーフィルの関係を示す図である。
また、コア材621を含む半田ボール625を用いずに、コア材を含まない半田ボール620Cを用いつつ、配線基板100と光半導体チップ200との間にスペーサを介在させて距離を安定させてもよい。スペーサは、例えば光半導体チップ200の4隅に配置することができる。
また、XY平面内で導電材620GWの分布に対称性を持たせることで配線基板100と光半導体チップ200との間の距離のばらつきを抑制することもできる。例えば、図8に示すように、導電材620GWが90°回転の点対称で配置されていてもよい。また、図9に示すように、導電材620GWが180°回転の点対称で配置されていてもよい。図8は、第1の実施形態の第1の変形例における、配線基板、導電材及びアンダーフィルの関係を示す図である。図9は、第1の実施形態の第2の変形例における、配線基板、導電材及びアンダーフィルの関係を示す図である。
なお、導電材620Bは、導電材620GWを形成するリフローにおいて、表面張力によって球体に近づこうとする。このため、半田ペースト620Aのレイアウトは、形成しようとする導電材620GWのレイアウト及び溶融した導電材620Bの表面張力を考慮して決定することが好ましい。例えば、半田ペースト620Aは、一定の幅を持たせて形成することができる。
図10及び図11に示すように、電極パッド240が最近接で並ぶ方向において、電極パッド240Hと電極パッド240Lとの間に配置された複数の電極パッド240Gが連結して帯状の電極パッド240GWが形成されていてもよい。また、複数の電極パッド120Gにおいても、複数の電極パッド120Gが連結して帯状の電極パッド120GWが形成され、電極パッド120GWが電極パッド240GWに電気的に接続されていてもよい。図10は、第1の実施形態の第3の変形例における、光半導体チップ200の構造を示す下面図である。図11は、第1の実施形態の第3の変形例に係る光モジュールの構造を示す平面図である。電極パッド240GWは第3の電極パッドの一例であり、電極パッド120GWは第6の電極パッドの一例である。
第1の実施形態の第1の変形例、第2の変形例、第2の実施形態においても、第1の実施形態の第31の変形例と同様に、帯状の電極パッド240GWが形成されていてもよく、帯状の電極パッド120GWが形成されていてもよい。
以上、好ましい実施の形態等について詳説したが、上述した実施の形態等に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態等に種々の変形及び置換を加えることができる。
例えば、第1の電極パッド、第1の導電材及び第4の電極パッドを通じて伝送される信号は差動信号でなくてもよい。
以下、本開示の諸態様を付記としてまとめて記載する。
(付記1)
第1の電極パッドと、第2の電極パッドと、前記第1の電極パッドと前記第2の電極パッドとの間に配置された第3の電極パッドと、を備えた光半導体チップと、
第4の電極パッドと、第5の電極パッドと、前記第4の電極パッドと前記第5の電極パッドとの間に配置された第6の電極パッドと、備え、前記光半導体チップがフリップチップ実装された配線基板と、
前記第1の電極パッドと前記第4の電極パッドとを接続する第1の導電材と、
前記第2の電極パッドと前記第5の電極パッドとを接続する第2の導電材と、
前記第1の導電材と前記第2の導電材との間に配置され、前記第3の電極パッドと前記第6の電極パッドとを接続する第3の導電材と、
前記光半導体チップと前記配線基板との間で、前記第3の導電材の前記第2の導電材側に設けられた樹脂と、
を有することを特徴とする光モジュール。
(付記2)
前記光半導体チップは、前記第3の電極パッドを複数有し、
前記配線基板は、前記第6の電極パッドを複数有し、
前記第3の導電材は、複数の前記第3の電極パッドと複数の前記第6の電極パッドとを接続していることを特徴とする付記1に記載の光モジュール。
(付記3)
前記第2の導電材は前記樹脂に接触し、前記第1の導電材は前記樹脂に非接触であることを特徴とする付記1又は2に記載の光モジュール。
(付記4)
前記第1の導電材及び前記第2の導電材はコア材を有することを特徴とする付記1乃至3のいずれか1項に記載の光モジュール。
(付記5)
前記配線基板は、前記第4の電極パッドに接続されたコプレーナ線路を有することを特徴とする付記1乃至4のいずれか1項に記載の光モジュール。
(付記6)
前記第1の導電材を介して伝送される信号の第1の速度が、前記第2の導電材を介して伝送される信号の第2の速度よりも速いことを特徴とする付記1乃至5のいずれか1項に記載の光モジュール。
(付記7)
前記第3の電極パッド、前記第6の電極パッド及び前記第3の導電材は接地されることを特徴とする付記1乃至6のいずれか1項に記載の光モジュール。
(付記8)
前記第1の導電材を介して伝送される信号の周波数が最大30GHz以上であることを特徴とする付記1乃至7のいずれか1項に記載の光モジュール。
(付記9)
第1の電極パッドと、第2の電極パッドと、前記第1の電極パッドと前記第2の電極パッドとの間に配置された第3の電極パッドと、を備えた光半導体チップを準備する工程と、
第4の電極パッドと、第5の電極パッドと、前記第4の電極パッドと前記第5の電極パッドとの間に配置された第6の電極パッドと、備え、前記光半導体チップがフリップチップ実装された配線基板を準備する工程と、
前記第1の電極パッドと前記第4の電極パッドとを接続する第1の導電材を形成する工程と、
前記第2の電極パッドと前記第5の電極パッドとを接続する第2の導電材を形成する工程と、
前記第1の導電材と前記第2の導電材との間に、前記第3の電極パッドと前記第6の電極パッドとを接続する第3の導電材を形成する工程と、
前記光半導体チップと前記配線基板との間で、前記第3の導電材の前記第2の導電材側に樹脂を形成する工程と、
を有することを特徴とする光モジュールの製造方法。
(付記10)
前記光半導体チップは、前記第3の電極パッドを複数有し、
前記配線基板は、前記第6の電極パッドを複数有し、
前記第3の導電材により、複数の前記第3の電極パッドと複数の前記第6の電極パッドとを接続することを特徴とする付記9に記載の光モジュールの製造方法。
(付記11)
前記樹脂を、前記第2の導電材に接触し、前記第1の導電材には非接触となるように形成することを特徴とする付記9又は10に記載の光モジュールの製造方法。
(付記12)
前記第1の導電材及び前記第2の導電材はコア材を有することを特徴とする付記9乃至11のいずれか1項に記載の光モジュールの製造方法。
(付記13)
前記配線基板は、前記第4の電極パッドに接続されたコプレーナ線路を有することを特徴とする付記9乃至12のいずれか1項に記載の光モジュールの製造方法。
(付記14)
前記第1の導電材を介して伝送される信号の第1の速度が、前記第2の導電材を介して伝送される信号の第2の速度よりも速いことを特徴とする付記9乃至13のいずれか1項に記載の光モジュールの製造方法。
(付記15)
前記第3の電極パッド、前記第6の電極パッド及び前記第3の導電材は接地されることを特徴とする付記9乃至14のいずれか1項に記載の光モジュールの製造方法。
(付記16)
前記第1の導電材を介して伝送される信号の周波数が最大30GHz以上であることを特徴とする付記9乃至15のいずれか1項に記載の光モジュールの製造方法。
1、2:光モジュール
100:配線基板
120H、120L、120G、240H、240L、240G:電極パッド
190:アンダーフィル
200:光半導体チップ
620A、629:半田ペースト
620C、625:半田ボール
620H、620L、620G、620GW、625H、625L、625G:導電材
621H、621L、621G:コア材

Claims (6)

  1. 複数の第1の電極パッドと、複数の第2の電極パッドと、前記複数の第1の電極パッドと前記複数の第2の電極パッドとの間に配置された複数の第3の電極パッドと、を備えた光半導体チップと、
    複数の第4の電極パッドと、複数の第5の電極パッドと、前記複数の第4の電極パッドと前記複数の第5の電極パッドとの間に配置された複数の第6の電極パッドと、備え、前記光半導体チップがフリップチップ実装された配線基板と、
    それぞれ、前記複数の第1の電極パッドのうちの一つと前記複数の第4の電極パッドのうちの一つとを接続する複数の第1の導電材と、
    それぞれ、前記複数の第2の電極パッドのうちの一つと前記複数の第5の電極パッドのうちの一つとを接続する複数の第2の導電材と、
    前記複数の第1の導電材と前記複数の第2の導電材との間に配置された1又は2以上の第3の導電材と、
    前記光半導体チップと前記配線基板との間で、前記第3の導電材の前記第2の導電材側に設けられた樹脂と、
    を有し、
    前記第2の導電材は前記樹脂に接触し、前記第1の導電材は前記樹脂に非接触であり、
    前記光半導体チップは、前記第3の導電材の前記第1の導電材側に設けられた複数の第7の電極パッドを有し、
    前記配線基板は、前記第3の導電材の前記第1の導電材側に設けられた複数の第8の電極パッドを有し、
    前記第3の導電材の前記第1の導電材側に設けられ、それぞれ、前記複数の第7の電極パッドのうちの一つと前記複数の第8の電極パッドのうちの一つとを接続する複数の第4の導電材を有し、
    前記1又は2以上の第3の導電材の各々は、前記複数の第3の電極パッドと前記複数の第6の電極パッドとを接続し、
    前記第1の導電材を介して伝送される信号の第1の速度が、前記第2の導電材を介して伝送される信号の第2の速度よりも速く、
    前記複数の第1の導電材、前記複数の第2の導電材及び前記第4の導電材のうちの同一直線上にない少なくとも3個で、すべてではない導電材はコア材を有し、
    前記コア材の融点は半田の融点よりも高いことを特徴とする光モジュール。
  2. 前記配線基板は、前記第4の電極パッドに接続されたコプレーナ線路を有することを特徴とする請求項1に記載の光モジュール。
  3. 前記第3の電極パッド、前記第6の電極パッド及び前記第3の導電材は接地されることを特徴とする請求項1又は2に記載の光モジュール。
  4. 前記コア材を有する少なくとも3個の導電材の数は、前記第3の導電材の前記第1の導電材側において、前記第3の導電材の前記第2の導電材側よりも少ないことを特徴とする請求項1乃至のいずれか1項に記載の光モジュール。
  5. 複数の第1の電極パッドと、複数の第2の電極パッドと、前記複数の第1の電極パッドと前記複数の第2の電極パッドとの間に配置された複数の第3の電極パッドと、を備えた光半導体チップを準備する工程と、
    複数の第4の電極パッドと、複数の第5の電極パッドと、前記複数の第4の電極パッドと前記複数の第5の電極パッドとの間に配置された複数の第6の電極パッドと、備え、前記光半導体チップがフリップチップ実装された配線基板を準備する工程と、
    それぞれ、前記複数の第1の電極パッドのうちの一つと前記複数の第4の電極パッドのうちの一つとを接続する複数の第1の導電材を形成する工程と、
    それぞれ、前記複数の第2の電極パッドのうちの一つと前記複数の第5の電極パッドのうちの一つとを接続する複数の第2の導電材を形成する工程と、
    前記複数の第1の導電材と前記複数の第2の導電材との間に、1又は2以上の第3の導電材を形成する工程と、
    前記光半導体チップと前記配線基板との間で、前記第3の導電材の前記第2の導電材側に樹脂を、前記第2の導電材に接触し、前記第1の導電材には非接触となるように形成する工程と、
    を有し、
    前記光半導体チップは、前記第3の導電材の前記第1の導電材側に設けられる複数の第7の電極パッドを有し、
    前記配線基板は、前記第3の導電材の前記第1の導電材側に設けられる複数の第8の電極パッドを有し、
    前記第3の導電材の前記第1の導電材側に、それぞれ、前記複数の第7の電極パッドのうちの一つと前記複数の第8の電極パッドのうちの一つとを接続する複数の第4の導電材を形成する工程を有し、
    前記1又は2以上の第3の導電材の各々は、前記複数の第3の電極パッドと前記複数の第6の電極パッドとを接続し、
    前記第1の導電材を介して伝送される信号の第1の速度が、前記第2の導電材を介して伝送される信号の第2の速度よりも速く、
    前記複数の第1の導電材、前記複数の第2の導電材及び前記第4の導電材のうちの同一直線上にない少なくとも3個で、すべてではない導電材はコア材を有し、
    前記コア材の融点は半田の融点よりも高いことを特徴とする光モジュールの製造方法。
  6. 前記コア材を有する少なくとも3個の導電材の数は、前記第3の導電材の前記第1の導電材側において、前記第3の導電材の前記第2の導電材側よりも少ないことを特徴とする請求項に記載の光モジュールの製造方法。
JP2019039752A 2019-03-05 2019-03-05 光モジュール及びその製造方法 Active JP7298195B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019039752A JP7298195B2 (ja) 2019-03-05 2019-03-05 光モジュール及びその製造方法
US16/806,256 US11495589B2 (en) 2019-03-05 2020-03-02 Optical module and manufacturing method of optical module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019039752A JP7298195B2 (ja) 2019-03-05 2019-03-05 光モジュール及びその製造方法

Publications (2)

Publication Number Publication Date
JP2020144192A JP2020144192A (ja) 2020-09-10
JP7298195B2 true JP7298195B2 (ja) 2023-06-27

Family

ID=72335617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019039752A Active JP7298195B2 (ja) 2019-03-05 2019-03-05 光モジュール及びその製造方法

Country Status (2)

Country Link
US (1) US11495589B2 (ja)
JP (1) JP7298195B2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3109466B1 (fr) * 2020-04-16 2024-05-17 St Microelectronics Grenoble 2 Dispositif de support d’une puce électronique et procédé de fabrication correspondant

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541397B1 (ko) 1998-06-25 2006-05-09 삼성전자주식회사 절연된 더미 솔더 볼을 갖는 비지에이 패키지
KR100652133B1 (ko) 2005-12-20 2006-11-30 서울옵토디바이스주식회사 플립칩 구조의 발광 소자
US20070178667A1 (en) 2006-01-31 2007-08-02 Stats Chippac Ltd. Wafer level chip scale package system
US20070205520A1 (en) 2006-03-02 2007-09-06 Megica Corporation Chip package and method for fabricating the same
JP2009500820A (ja) 2005-06-29 2009-01-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ アセンブリを製造する方法及びアセンブリ
JP2011124248A (ja) 2009-12-08 2011-06-23 Nichia Corp 発光装置の製造方法
US20120168928A1 (en) 2008-04-10 2012-07-05 Semtech Corporation Chip assembly with frequency extending device
JP2017199937A (ja) 2017-08-01 2017-11-02 新光電気工業株式会社 電子部品内蔵基板及びその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964238A (ja) 1995-08-21 1997-03-07 Oki Electric Ind Co Ltd 半導体チップの実装構造及び方法
JP2000269384A (ja) 1999-03-12 2000-09-29 Nec Corp マイクロ波・ミリ波回路装置及びその製造方法
US6639322B1 (en) * 2001-09-17 2003-10-28 Applied Micro Circuits Corporation Flip-chip transition interface structure
JP2009188026A (ja) * 2008-02-04 2009-08-20 Hitachi Metals Ltd 電子部品
US8487430B1 (en) * 2010-01-21 2013-07-16 Semtech Corporation Multi-layer high-speed integrated circuit ball grid array package and process
US9607863B1 (en) 2013-08-09 2017-03-28 Altera Corporation Integrated circuit package with vacant cavity
US10502987B2 (en) * 2015-04-07 2019-12-10 Lumentum Operations Llc High bandwidth RF or microwave interconnects for optical modulators
US9978707B1 (en) * 2017-03-23 2018-05-22 Delphi Technologies, Inc. Electrical-device adhesive barrier
DE112017007887T5 (de) * 2017-09-29 2020-05-07 Intel Corporation Antennenpackage mit kugel-anbringungs-array zum verbinden von antennen- und basissubstraten

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541397B1 (ko) 1998-06-25 2006-05-09 삼성전자주식회사 절연된 더미 솔더 볼을 갖는 비지에이 패키지
JP2009500820A (ja) 2005-06-29 2009-01-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ アセンブリを製造する方法及びアセンブリ
KR100652133B1 (ko) 2005-12-20 2006-11-30 서울옵토디바이스주식회사 플립칩 구조의 발광 소자
US20070178667A1 (en) 2006-01-31 2007-08-02 Stats Chippac Ltd. Wafer level chip scale package system
US20070205520A1 (en) 2006-03-02 2007-09-06 Megica Corporation Chip package and method for fabricating the same
US20120168928A1 (en) 2008-04-10 2012-07-05 Semtech Corporation Chip assembly with frequency extending device
JP2011124248A (ja) 2009-12-08 2011-06-23 Nichia Corp 発光装置の製造方法
JP2017199937A (ja) 2017-08-01 2017-11-02 新光電気工業株式会社 電子部品内蔵基板及びその製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
R. Windemuth et al.,"New Flipchip Technology",2012 4th Electronic System-Integration Technology Conference,米国,IEEE,2012年07月17日,pp.1-6
本多 進,メカニカル接続技術,プリント回路技術便覧 第3版,第3版,日刊工業新聞社 千野 俊猛,pp. 1158-1166

Also Published As

Publication number Publication date
US20200286874A1 (en) 2020-09-10
US11495589B2 (en) 2022-11-08
JP2020144192A (ja) 2020-09-10

Similar Documents

Publication Publication Date Title
JP6524986B2 (ja) 高周波モジュール、アンテナ付き基板、及び高周波回路基板
JP6449760B2 (ja) 半導体装置
US6008534A (en) Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
JP5287390B2 (ja) 半導体装置、伝送システム、半導体装置の製造方法及び伝送システムの製造方法
JP6643714B2 (ja) 電子装置及び電子機器
US11211315B2 (en) Semiconductor package with terminal pattern for increased channel density
CN113261097A (zh) 一种芯片封装装置、终端设备
US11937368B2 (en) Structure for circuit interconnects
JP7298195B2 (ja) 光モジュール及びその製造方法
US20100327452A1 (en) Mounting structure and method of manufacturing the same
US6566761B1 (en) Electronic device package with high speed signal interconnect between die pad and external substrate pad
US10212807B2 (en) Electrical interface for package and die
JP6465451B1 (ja) 電子回路
JP2020107878A (ja) 多層回路基板
US6812576B1 (en) Fanned out interconnect via structure for electronic package substrates
WO2017150060A1 (ja) 実装構造及びモジュール
US20120021599A1 (en) Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package
US20220375885A1 (en) Flip-chip ball grid array-type integrated circuit package for very high frequency operation
US7132748B2 (en) Semiconductor apparatus
CN118016638B (zh) 一种适用于晶圆级封装的低损耗宽带过渡结构
JP2012069772A (ja) 半導体装置およびその製造方法
US11869845B2 (en) Semiconductor package device and semiconductor wiring substrate thereof
JP2012182174A (ja) 電子回路、及び、電子回路の製造方法
JP2010141366A (ja) 半導体装置
JP3470052B2 (ja) 高周波用部品の接続構造

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211130

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220907

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220913

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230110

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230308

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230516

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230529

R150 Certificate of patent or registration of utility model

Ref document number: 7298195

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150