JP7248660B2 - 裏面シリサイド化によるバルク層転写処理 - Google Patents

裏面シリサイド化によるバルク層転写処理 Download PDF

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JP7248660B2
JP7248660B2 JP2020517136A JP2020517136A JP7248660B2 JP 7248660 B2 JP7248660 B2 JP 7248660B2 JP 2020517136 A JP2020517136 A JP 2020517136A JP 2020517136 A JP2020517136 A JP 2020517136A JP 7248660 B2 JP7248660 B2 JP 7248660B2
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bulk semiconductor
dielectric layer
layer
semiconductor wafer
trench isolation
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JP2020535647A5 (enExample
JP2020535647A (ja
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シナン・ゴクテペリ
ジョージ・ピート・イムサーン
スティーヴン・アラン・ファネリ
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クアルコム,インコーポレイテッド
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass H10D
    • H01L25/117Stacked arrangements of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/20Inductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/68Capacitors having no potential barriers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151Manufacturing their isolation regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2020517136A 2017-09-29 2018-08-27 裏面シリサイド化によるバルク層転写処理 Active JP7248660B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762565495P 2017-09-29 2017-09-29
US62/565,495 2017-09-29
US15/975,434 2018-05-09
US15/975,434 US10559520B2 (en) 2017-09-29 2018-05-09 Bulk layer transfer processing with backside silicidation
PCT/US2018/048125 WO2019067129A1 (en) 2017-09-29 2018-08-27 MASSIVE LAYER TRANSFER TREATMENT WITH SILICIURATION ON THE REAR PANEL

Publications (3)

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JP2020535647A JP2020535647A (ja) 2020-12-03
JP2020535647A5 JP2020535647A5 (enExample) 2021-09-24
JP7248660B2 true JP7248660B2 (ja) 2023-03-29

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US (1) US10559520B2 (enExample)
EP (1) EP3688795B1 (enExample)
JP (1) JP7248660B2 (enExample)
KR (1) KR102675753B1 (enExample)
CN (1) CN111133565B (enExample)
CA (1) CA3073721A1 (enExample)
WO (1) WO2019067129A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199461B2 (en) * 2015-10-27 2019-02-05 Texas Instruments Incorporated Isolation of circuit elements using front side deep trench etch
US10615252B2 (en) * 2018-08-06 2020-04-07 Nxp Usa, Inc. Device isolation
WO2021102789A1 (en) * 2019-11-28 2021-06-03 Yangtze Memory Technologies Co., Ltd. Local word line driver device, memory device, and fabrication method thereof
US11568052B2 (en) 2020-05-31 2023-01-31 Microsoft Technology Licensing, Llc Undetectable sandbox for malware
CN111883476B (zh) * 2020-09-18 2023-04-14 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US11721883B2 (en) * 2021-02-25 2023-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with antenna and method of forming the same
US20240008290A1 (en) * 2022-06-30 2024-01-04 Intel Corporation Back-end-of-line 2d memory cell
CN120565491B (zh) * 2025-07-31 2025-10-10 杭州富芯半导体有限公司 一种半导体结构、制备方法及半导体器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278646A (ja) 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
US20120091593A1 (en) 2010-10-14 2012-04-19 International Business Machines Corporation Structure and method for simultaneously forming a through silicon via and a deep trench structure
JP2014207252A (ja) 2011-08-17 2014-10-30 株式会社村田製作所 半導体装置およびその製造方法ならびに携帯電話機
JP2015050339A (ja) 2013-09-02 2015-03-16 ソニー株式会社 半導体装置およびその製造方法
JP2015527733A (ja) 2012-07-09 2015-09-17 クアルコム,インコーポレイテッド 集積回路のウェハ裏面の層からの基板貫通ビアの統合

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3681862D1 (de) * 1985-08-23 1991-11-14 Siemens Ag Verfahren zur herstellung einer hochsperrenden diodenanordnung auf der basis von a-si:h fuer bildsensorzeilen.
JP3587537B2 (ja) * 1992-12-09 2004-11-10 株式会社半導体エネルギー研究所 半導体装置
JP4289146B2 (ja) 2003-03-27 2009-07-01 セイコーエプソン株式会社 三次元実装型半導体装置の製造方法
JP2006108520A (ja) 2004-10-08 2006-04-20 Sharp Corp 半導体装置及び半導体装置の製造方法
JP4869664B2 (ja) 2005-08-26 2012-02-08 本田技研工業株式会社 半導体装置の製造方法
US7285477B1 (en) 2006-05-16 2007-10-23 International Business Machines Corporation Dual wired integrated circuit chips
JP2007335642A (ja) 2006-06-15 2007-12-27 Fujifilm Corp パッケージ基板
TWI382515B (zh) * 2008-10-20 2013-01-11 鈺程科技股份有限公司 無線收發模組
JP4945545B2 (ja) 2008-11-10 2012-06-06 株式会社日立製作所 半導体装置の製造方法
US8299583B2 (en) 2009-03-05 2012-10-30 International Business Machines Corporation Two-sided semiconductor structure
US8455875B2 (en) * 2010-05-10 2013-06-04 International Business Machines Corporation Embedded DRAM for extremely thin semiconductor-on-insulator
US8779559B2 (en) * 2012-02-27 2014-07-15 Qualcomm Incorporated Structure and method for strain-relieved TSV
US20130249011A1 (en) * 2012-03-22 2013-09-26 Texas Instruments Incorporated Integrated circuit (ic) having tsvs and stress compensating layer
US9093462B2 (en) 2013-05-06 2015-07-28 Qualcomm Incorporated Electrostatic discharge diode
CN104241279B (zh) * 2013-06-18 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种集成电路及其制造方法
CN104241267B (zh) * 2013-06-18 2017-08-01 中芯国际集成电路制造(上海)有限公司 一种集成电路及其制造方法
US9252077B2 (en) * 2013-09-25 2016-02-02 Intel Corporation Package vias for radio frequency antenna connections
EP2887387A1 (en) * 2013-12-20 2015-06-24 Nxp B.V. Semiconductor device and associated method
EP2913847B1 (en) * 2014-02-28 2018-04-18 LFoundry S.r.l. Method of fabricating a semiconductor device and semiconductor product
US9368479B2 (en) * 2014-03-07 2016-06-14 Invensas Corporation Thermal vias disposed in a substrate proximate to a well thereof
US9324632B2 (en) * 2014-05-28 2016-04-26 Globalfoundries Inc. Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
JP2015228473A (ja) 2014-06-03 2015-12-17 パナソニックIpマネジメント株式会社 半導体装置およびその製造方法
KR102235613B1 (ko) * 2014-11-20 2021-04-02 삼성전자주식회사 Mos 커패시터를 구비하는 반도체 소자
US9673084B2 (en) * 2014-12-04 2017-06-06 Globalfoundries Singapore Pte. Ltd. Isolation scheme for high voltage device
US9570494B1 (en) * 2015-09-29 2017-02-14 Semiconductor Components Industries, Llc Method for forming a semiconductor image sensor device
US9755029B1 (en) 2016-06-22 2017-09-05 Qualcomm Incorporated Switch device performance improvement through multisided biased shielding
US20180138081A1 (en) * 2016-11-15 2018-05-17 Vanguard International Semiconductor Corporation Semiconductor structures and method for fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278646A (ja) 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
US20120091593A1 (en) 2010-10-14 2012-04-19 International Business Machines Corporation Structure and method for simultaneously forming a through silicon via and a deep trench structure
JP2014207252A (ja) 2011-08-17 2014-10-30 株式会社村田製作所 半導体装置およびその製造方法ならびに携帯電話機
JP2015527733A (ja) 2012-07-09 2015-09-17 クアルコム,インコーポレイテッド 集積回路のウェハ裏面の層からの基板貫通ビアの統合
JP2015050339A (ja) 2013-09-02 2015-03-16 ソニー株式会社 半導体装置およびその製造方法

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Publication number Publication date
US20190103339A1 (en) 2019-04-04
EP3688795C0 (en) 2025-06-18
BR112020005804A2 (pt) 2020-09-24
CN111133565A (zh) 2020-05-08
US10559520B2 (en) 2020-02-11
WO2019067129A1 (en) 2019-04-04
KR20200057714A (ko) 2020-05-26
JP2020535647A (ja) 2020-12-03
EP3688795B1 (en) 2025-06-18
EP3688795A1 (en) 2020-08-05
KR102675753B1 (ko) 2024-06-14
CN111133565B (zh) 2023-10-13
CA3073721A1 (en) 2019-04-04

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