Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L25/11—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass H10D
  • H01L25/117—Stacked arrangements of devices
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/20—Inductors
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0151—Manufacturing their isolation regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• the present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to bulk layer transfer processing with backside silicidation.
• Designing mobile radio frequency (RF) chips is complicated by added circuit functions for supporting communication enhancements.
• Designing these mobile RF transceivers may include using semiconductor on insulator technology.
• Semiconductor on insulator (SOI) technology replaces conventional semiconductor (e.g., silicon) substrates with a layered semiconductor-insulator- semiconductor substrate for reducing parasitic capacitance and improving performance.
• SOI-based devices differ from conventional, silicon-built devices because a silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer.
• a reduced thickness BOX layer may not sufficiently reduce artificial harmonics caused by the proximity of an active device on the SOI layer and an SOI substrate supporting the BOX layer.
• CMOS complementary metal oxide semiconductor
• RF radio frequency
• SOI substrates may provide some protection against artificial harmonics in mobile RF transceivers
• SOI substrates are very expensive.
• increasing device isolation and reducing RF loss may involve expensive handle wafers.
• a CMOS switch device may be physically bonded to a high resistivity (FIR) handle wafer, such as HR-silicon or sapphire.
• FIR high resistivity
• HR-silicon or sapphire handle wafer While the increased spatial separation of the switch device from the underlying substrate dramatically improves the RF performance of the CMOS switch, using HR-silicon or sapphire handle wafer dramatically drives up cost. That is, using SOI wafers and handle substrates is quite expensive relative to the cost of a bulk semiconductor wafer.
• a radio frequency integrated circuit may include a bulk
• the RFIC may include a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die.
• the RFIC may also include a contact layer on the second-side of the bulk semiconductor die.
• the RFIC may further include a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.
• a method of constructing a radio frequency (RF) integrated circuit may include fabricating a first transistor on a first-side of a bulk semiconductor wafer. The method may also include forming a first deep trench isolation region in the bulk semiconductor wafer, proximate the first transistor. The method may also include depositing a first-side dielectric layer on the first transistor. The method may further include bonding a handle substrate to the first-side dielectric layer. The method may also include exposing the first deep trench isolation region at a second-side of the bulk semiconductor wafer. The method may further include depositing a contact layer on the second-side of the bulk semiconductor wafer and on exposed sidewalls of the first deep trench isolation region.
• RF radio frequency
• a radio frequency (RF) front end module may include a wireless transceiver.
• the wireless transceiver may include a bulk semiconductor die including a first transistor on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die.
• the wireless transceiver may also include a contact layer on the second-side of the bulk semiconductor die, and a second-side dielectric layer on the contact layer.
• the first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.
• the RF front end module may also include an antenna coupled to an output of the wireless transceiver.
• FIGURE 1 is a schematic diagram of a wireless device having a wireless local area network module and a radio frequency (RF) front end module for a chipset.
• RF radio frequency
• FIGURE 2 shows a cross-sectional view of a radio frequency integrated circuit (RFIC), including an RF semiconductor on insulator (SOI) device.
• RFIC radio frequency integrated circuit
• SOI RF semiconductor on insulator
• FIGURE 3 is a cross-sectional view of a radio frequency integrated circuit (RFIC) fabricated using a bulk semiconductor layer transfer process according to aspects of the present disclosure.
• FIGURE 4 is a cross-sectional view of a radio frequency integrated circuit (RFIC) having a bulk semiconductor die including a contact layer on a backside of the bulk semiconductor die, according to aspects of the present disclosure.
• RFIC radio frequency integrated circuit
• FIGURES 5A - 5G illustrate a process for fabricating the RFIC in FIGURE 4, according to aspects of the present disclosure.
• FIGURE 6 is a process flow diagram illustrating a method of constructing a radio frequency integrated circuit (RFIC) using a bulk semiconductor layer transfer process according to aspects of the present disclosure.
• RFIC radio frequency integrated circuit
• FIGURE 7 is a block diagram showing an exemplary wireless
• FIGURE 8 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component according to one configuration of the present disclosure.
• the term “and/or” is intended to represent an “inclusive OR”, and the use of the term “or” is intended to represent an "exclusive OR”.
• the term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary configurations.
• the term “coupled” used throughout this description means "connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches.
• the term “proximate” used throughout this description means
• Designing mobile radio frequency (RF) transceivers may include using semiconductor on insulator technology.
• Semiconductor on insulator (SOI) technology replaces conventional silicon substrates with a layered semiconductor-insulator- semiconductor substrate for reducing parasitic capacitance and improving performance. While SOI-based devices differ from conventional, silicon-built devices by including a silicon junction above an electrical isolator, typically a buried oxide (BOX) layer, SOI- based devices are more expensive than conventional, silicon-built devices.
• SOI semiconductor on insulator
• BOX buried oxide
• a reduced thickness BOX layer may not sufficiently reduce artificial harmonics caused by the proximity of an active device on an SOI layer and an SOI substrate supporting the BOX layer.
• the active devices on the SOI layer may include high performance complementary metal oxide semiconductor (CMOS) transistors.
• CMOS complementary metal oxide semiconductor
• CMOS RF switch technologies are currently manufactured using SOI substrates.
• RFFE radio frequency front end
• a process for fabricating an RFFE module therefore, involves the costly integration of an SOI wafer for supporting these high performances CMOS RF switch technologies.
• supporting future RF performance enhancements involves increasing device isolation while reducing RF loss.
• an RF device e.g., an RF switch device
• SOI wafers having trap rich regions cost about twice as much as regular SOI wafers.
• a layer transfer process may physically bond an RF switch device (e.g., fabricated using an SOI wafer) to a high resistivity (HR) handle wafer (e.g., such as HR-silicon or sapphire).
• HR high resistivity
• Various aspects of the present disclosure provide techniques for bulk layer transfer processing with backside silicidation.
• the process flow for semiconductor fabrication of the integrated RF circuit may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes.
• FEOL front-end-of-line
• MOL middle-of-line
• BEOL back-end-of-line
• layer includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated.
• substrate may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced.
• the terms chip and die may be used interchangeably.
• a radio frequency integrated circuit includes a semiconductor device layer on a front-side of a bulk semiconductor die.
• a deep trench isolation region may extend from the front-side to a backside opposite the front-side of the bulk
• a silicide layer may be deposited on the backside of the bulk semiconductor die as a contact layer.
• the back side of the bulk semiconductor die may be supported by a backside dielectric layer (e.g., a second-side dielectric layer) distal from a front-side dielectric layer (e.g., a first-side dielectric layer) on the semiconductor device layer.
• the RFIC may also include a handle substrate on the front-side dielectric layer.
• the front-side and backside may each be referred to as a first-side or a second- side. In some cases, the front-side will be referred to as the first-side. In other cases, the backside will be referred to as the first-side.
• FIGURE 1 is a schematic diagram of a wireless device (e.g., a cellular phone or a smartphone) having a wireless local area network module and a radio frequency (RF) front end module for a chipset.
• the wireless device 100 may include a wireless local area network (WLAN) (e.g., WiFi) module 150 and an RF front end module 170 for a chipset 110, which may be fabricated using a bulk semiconductor die, according to aspects of the present disclosure.
• the WiFi module 150 includes a first diplexer 160 communicably coupling an antenna 162 to a wireless local area network module (e.g., WLAN module 152).
• the RF front end module 170 includes a second diplexer 190 communicably coupling an antenna 192 to the wireless transceiver 120 (WTR) through a duplexer 180 (DUP).
• the wireless transceiver 120 and the WLAN module 152 of the WiFi module 150 are coupled to a modem (MSM, e.g., a baseband modem) 130 that is powered by a power supply 102 through a power management integrated circuit (PMIC) 140.
• the chipset 110 also includes capacitors 112 and 114, as well as an inductor(s) 116 to provide signal integrity.
• the PMIC 140, the modem 130, the wireless transceiver 120, and the WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate according to a clock 118.
• the geometry and arrangement of the various inductor and capacitor components in the chipset 110 may reduce the electromagnetic coupling between the components.
• the wireless transceiver 120 of the wireless device 100 generally includes a mobile RF transceiver to transmit and receive data for two-way communication.
• a mobile RF transceiver may include a transmit section for data transmission and a receive section for data reception.
• the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal having the proper output power level, and transmit the amplified RF signal via the antenna 192 to a base station.
• PA power amplifier
• the receive section may obtain a received RF signal via the antenna 192 and may amplify the received RF signal using a low noise amplifier (LNA) and process the received RF signal to recover data sent by the base station in a communication signal.
• LNA low noise amplifier
• the wireless transceiver 120 may include one or more circuits for amplifying these communication signals.
• the amplifier circuits e.g., LNA/PA
• the amplifier circuits may include one or more amplifier stages that may have one or more driver stages and one or more amplifier output stages.
• Each of the amplifier stages includes one or more transistors configured in various ways to amplify the communication signals.
• the wireless transceiver 120 and the RF front end module 170 may be implemented using a layer transfer process to separate the active device from a substrate as shown in FIGURE 2.
• FIGURE 2 shows a cross-sectional view of a radio frequency (RF) integrated circuit 200, including an RF semiconductor on insulator (SOI) device, which may be fabricated using a layer transfer process.
• RF radio frequency
• SOI RF semiconductor on insulator
• an RF device includes an active device 210 on an insulator layer 220, which is initially supported by a sacrificial substrate 201.
• the RF device also includes interconnects 250 coupled to the active device 210 within a first dielectric layer 204.
• a handle substrate 202 is bonded to the first dielectric layer 204 of the RF device for enabling removal of the sacrificial substrate 201.
• Removal of the sacrificial substrate 201 using the layer transfer process enables high-performance, low-parasitic RF devices by increasing the dielectric thickness of, for example, the first dielectric layer 204. That is, a parasitic capacitance of the RF device is proportional to the dielectric thickness, which determines the distance between the active device 210 and the handle substrate 202.
• the active device 210 on the BOX layer 220 may be a complementary metal oxide semiconductor (CMOS) transistor.
• CMOS complementary metal oxide semiconductor
• the RFFE module 170 (FIGURE 1) may rely on these high performance CMOS RF technologies for successful operation.
• FIGURE 3 is a cross-sectional view of a radio frequency integrated circuit (RFIC) fabricated using a bulk semiconductor layer transfer process according to aspects of the present disclosure.
• an RF integrated circuit 300 includes an active device 310 having a gate, source/drain (S/D) regions, and a channel region between the source/drain regions, each formed on a front-side of a bulk semiconductor wafer 320.
• an active device layer including the source/drain and channel regions is not supported by a buried oxide (BOX) layer.
• BOX buried oxide
• the active device 310 may be a first active/passive device, as well as a second active/passive device.
• the RF integrated circuit 300 also includes middle-of-line (MOL)/back-end- of-line (BEOL) interconnects coupled to the source/drain regions of the active device 310.
• MOL middle-of-line
• BEOL back-end- of-line
• the MOL/BEOL layers may be referred to as first-side (e.g., front- side) layers.
• second-side e.g., backside
• a front-side metallization layer Ml is coupled to the source/drain regions of the active device 310 and arranged in a front-side dielectric layer 304.
• a handle substrate 302 is coupled to the front-side dielectric layer 304.
• a backside dielectric 340 is adjacent to and possibly supports the bulk semiconductor wafer 320.
• a backside metallization layer e.g., a second-side metallization layer
• DTI deep trench isolation
• semiconductor wafer 320 as further illustrated in FIGURE 4.
• FIGURE 4 is a cross-sectional view of a radio frequency integrated circuit (RFIC) having a bulk semiconductor die including a contact layer on a backside of the bulk semiconductor die, according to aspects of the present disclosure.
• RFIC radio frequency integrated circuit
• an RF integrated circuit 400 includes a first active device 410, a second active device 412, and a third active device 414, each having a gate (G), source/drain (S/D) regions, and a channel (C) region between the source/drain regions, each formed on a front-side of a bulk semiconductor wafer 420 (e.g., a bulk silicon wafer).
• a bulk semiconductor wafer 420 e.g., a bulk silicon wafer.
• an active device layer including the source/drain and channel regions of the active devices is not supported by a buried oxide (BOX) layer.
• the first active device 410 may be a first active/passive device, as well as a second active/passive device, such as the second active device 412.
• the active devices e.g., 410, 412, and 414.
• the active devices s may include, but are not limited to, planar field effect transistors (FETs), fin-type FETs (FinFETs), nanowire FETs, or other like FETs.
• the RF integrated circuit 400 also includes MOL interconnects (M0) as well as BEOL interconnects (Ml) coupled to the gate as well as the source/drain regions of the active devices (e.g., 410, 412, and 414).
• the MOL interconnects may include trench interconnects (e.g., CA, CB) and vias (e.g., V0) for coupling active devices formed during a front-end-of-line to metallization layers formed during the back-end-of-line processing.
• an MOL interconnect M0 is coupled to a gate contact (e.g., a poly contact) of the gate of the first active device 410 and arranged in a front-side dielectric layer 404.
• a handle wafer 402 (handle substrate) is coupled to the front-side dielectric layer 404.
• a backside dielectric layer 440 is adjacent to and possibly supports the bulk semiconductor wafer 420.
• a backside metallization layer (e.g., a second-side metallization layer) is coupled to the front-side MOL zero interconnect M0 through a trench interconnect 450.
• the trench interconnect 450 extends through a first deep trench isolation (DTI) region 430, from the front-side to the backside of the bulk semiconductor wafer 420.
• DTI deep trench isolation
• the backside metallization may also be coupled to a backside contact layer 460.
• the first DTI region 430 extends though the backside contact layer 460 and into the backside dielectric layer 440.
• a second deep trench isolation (DTI) region 432 extends though the backside contact layer 460 and into the backside dielectric layer 440.
• the backside contact layer 460 is deposited along the backside of the bulk semiconductor wafer 420.
• the backside contact layer 460 may be composed of a silicide material or other like conductive material.
• the backside contact layer 460 also contacts a portion of the first DTI region 430 that extends from the backside of the bulk semiconductor wafer 420.
• the backside dielectric layer 440 contacts the remaining portion of the first DTI region 430 that extends from the backside of the bulk semiconductor wafer 420.
• the layer transfer process shown in FIGURE 2 may be used with bulk semiconductor wafers to create CMOS products (e.g., a CMOS transistor) without using expensive SOI substrates, as shown in FIGURE 4.
• CMOS products e.g., a CMOS transistor
• FIGURES 5A - 5G CMOS transistor
• FIGURES 5A - 5G One aspect of the present disclosure uses a bulk layer transfer process with backside silicidation (FIGURE 6) to form an RF integrated circuit, for example, as shown in FIGURE 4.
• FIGURES 5A - 5G illustrate a process for fabricating the RF integrated circuit 400 of FIGURE 4, according to aspects of the present disclosure.
• FIGURE 5 A illustrates an initial step for forming the RF integrated circuit 400 of FIGURE 4. This process may begin with a complementary metal oxide semiconductor (CMOS) wafer, such as a bulk silicon wafer.
• CMOS front-end-of-line integration is performed on the bulk semiconductor wafer 420 to form the first active device 410, the second active device 412, and the third active device 414.
• the first active device 410 and the second active device 412 are separated by a shallow trench isolation (STI) region.
• the second active device 412 and the third active device 414 are separated by the second DTI region 432. It should be recognized that the first active device 410 and the second active device 412 by be separated by a DTI region to simplify the fabrication process of the RF integrated circuit 400.
• STI shallow trench isolation
• STI regions are used for active device separation, whereas the DTI regions are used for post layer transfer separation.
• a depth of the first DTI region 430 and the second DTI region 432 may be in the range of 0.4 to 4 micrometers, although the depth of the first DTI region 430 and the second DTI region 432 may be reduced for future processes.
• the DTI regions as well as the STI regions may be filed with a similar dielectric material, such as silicon dioxide (S1O2) and formed prior to the active devices.
• MOL processes connect the active devices to BEOL interconnect layers.
• a zero-layer interconnect M0 is coupled to the gate G of the first active device 410.
• a first BEOL interconnect Ml is coupled to the zero-layer interconnect M0.
• the first BEOL interconnect Ml is formed as part of a front-side BEOL process. This process is followed by depositing the front-side dielectric layer 404. Once the front-side dielectric layer 404 is deposited, the handle wafer 402 is bonded to the front-side dielectric layer 404.
• the handle wafer 402 can be a processed wafer or a bare wafer.
• FIGURE 5B illustrates a backgrind process of the bulk semiconductor wafer 420.
• This initial backgrind process is applied to the backside of the bulk semiconductor wafer 420, distal from the active device layer. This initial backgrind process may leave a surface variation of about 5 to 10 micrometers.
• the backgrind process continues in FIGURE 5C, in which a chemical mechanical polish (CMP) process is applied to the backside of the bulk semiconductor wafer 420.
• CMP chemical mechanical polish
• This CMP process may reduce the surface variation of the backside of the bulk semiconductor wafer 420 to a range of 0.1 micrometers to 0.4 micrometers, but preferably to 0.1 micrometers.
• This CMP process does not expose the first DTI region 430 or the second DTI region 432.
• the backgrind process may be applied to the backside of the bulk semiconductor wafer 420 with a surface variation of 5-10 microns.
• the surface variation may be reduced by polishing the backside of the bulk
• a silicon etch e.g., potassium hydroxide (KOH) or tetram ethyl ammonium hydroxide (TMAH)
• TMAH tetram ethyl ammonium hydroxide
• CMP chemical mechanical polish
• the silicon etch/CMP is performed on the backside of the bulk semiconductor wafer 420 for exposing a portion of the first DTI region 430 as well as the second DTI region 432.
• an etch stop layer may be formed in the bulk semiconductor wafer 420 for improving a planarity of the backside of the bulk semiconductor wafer 420.
• a post-layer transfer silicide layer may be deposited on an entire length of the backside of the bulk semiconductor wafer 420 for forming the backside contact layer 460, which is further described in FIGURE 5E.
• a trench interconnect 450 is formed through the first DTI region 430.
• the trench interconnect 450 is coupled to the front-side zero interconnect M0 in the front-side dielectric layer 404.
• the RF integrated circuit 400 is completed by forming a backside BEOL interconnect 452 and depositing the backside dielectric layer 440.
• the backside dielectric layer 440 is deposited on the backside of the bulk semiconductor wafer 420 and exposed sidewalls of the first DTI region 430 that extend from the backside of the bulk semiconductor wafer 420.
• the backside dielectric layer 440 is distal from the front-side dielectric layer 404.
• the backside BEOL interconnect 452 is coupled to the front-side zero interconnect M0 through the trench interconnect 450.
• FIGURE 6 is a process flow diagram illustrating a method 600 of a bulk layer transfer process with second-side (e.g., backside) silicidation for constructing a radio frequency integrated circuit (RFIC) according to an aspect of the present disclosure.
• a first transistor is fabricated on a first-side of a bulk semiconductor wafer.
• a first active device 410 is fabricated on a first-side of a bulk semiconductor wafer 420.
• a first deep trench isolation region is formed in the bulk semiconductor wafer, proximate the first transistor.
• the first DTI region 430 extends from the first-side to the second-side of the bulk semiconductor wafer 420.
• the method 600 may further include fabricating a second transistor on the first-side of the bulk semiconductor wafer.
• a second active device 412 is fabricated adjacent to the first active device 410.
• An STI region may be formed on the first-side of the bulk semiconductor wafer 420, between the first active device 410 and the second active device 412, prior to forming the active devices.
• a second DTI region 432 may be formed, extending from the first-side to the second-side of the bulk semiconductor wafer 420, proximate the second active device 412.
• the second DTI region 432 is formed between the second active device 412 and the third active device 414.
• a first-side dielectric layer is deposited on the first transistor.
• the front-side dielectric layer 404 is deposited on the first active device 410.
• a handle substrate is bonded to the first-side dielectric layer.
• the handle wafer 402 is bonded to the front-side dielectric layer 404.
• the first deep trench isolation region is exposed at a second-side of the bulk semiconductor wafer.
• the first DTI region 430 is exposed at a second-side of the bulk semiconductor wafer 420. The exposure of the first DTI region 430 may be performed by backgrinding the second-side of the bulk
• a contact layer is deposited on the second-side of the bulk semiconductor wafer and on exposed sidewalls of the first deep trench isolation region.
• the backside contact layer 460 is deposited on the backside of the bulk semiconductor wafer 420 using a backside silicide process.
• aspects of the present disclosure relate to using a bulk semiconductor (e.g., silicon) wafer for replacing SOI wafers. That is, aspects of the present disclosure employ inexpensive semiconductor wafers for forming a semiconductor device layer without the use of an expensive SOI wafer.
• One aspect of the present disclosure uses a backside silicidation process with layer transfer to form a bulk semiconductor wafer including an active device layer on a first-side and a contact layer on a second-side of the bulk semiconductor wafer.
• a post-layer transfer metallization process enables the formation of a second-side metallization coupled to a first-side metallization with a trench interconnect extending through a deep trench isolation region in the bulk semiconductor wafer.
• an RF integrated circuit including a bulk semiconductor die having an active/passive device on a first- side and a deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die, is described.
• the RF integrated circuit includes a first-side dielectric layer on the active/passive device.
• the RF integrated circuit structure also includes means for handling the RF integrated circuit on the first-side dielectric layer.
• the handling means may be the handle wafer, shown in FIGURE 3.
• the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.
• FIGURE 7 is a block diagram showing an exemplary wireless
• FIGURE 7 shows three remote units 720, 730, and 750 and two base stations 740. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units 720, 730, and 750 include IC devices 725A, 725C, and 725B that include the disclosed RFIC. It will be recognized that other devices may also include the disclosed RFIC, such as the base stations, switching devices, and network equipment.
• FIGURE 7 shows forward link signals 780 from the base station 740 to the remote units 720, 730, and 750 and reverse link signals 790 from the remote units 720, 730, and 750 to base stations 740.
• remote unit 720 is shown as a mobile telephone
• remote unit 730 is shown as a portable computer
• remote unit 750 is shown as a fixed location remote unit in a wireless local loop system.
• a remote unit may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading equipment, or other communications device that stores or retrieves data or computer instructions, or combinations thereof.
• FIGURE 7 illustrates remote units according to the aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the disclosed RFIC.
• FIGURE 8 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the RF devices disclosed above.
• a design workstation 800 includes a hard disk 801 containing operating system software, support files, and design software such as Cadence or OrCAD.
• the design workstation 800 also includes a display 802 to facilitate a circuit design 810 or an RFIC design 812.
• a storage medium 804 is provided for tangibly storing the circuit design 810 or the RFIC design 812.
• the circuit design 810 or the RFIC design 812 may be stored on the storage medium 804 in a file format such as GDSII or GERBER.
• the storage medium 804 may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation 800 includes a drive apparatus 803 for accepting input from or writing output to the storage medium 804. [0057] Data recorded on the storage medium 804 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic
• Providing data on the storage medium 804 facilitates the design of the circuit design 810 or the RFIC design 812 by decreasing the number of processes for designing semiconductor wafers.
• the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein.
• a machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein.
• software codes may be stored in a memory and executed by a processor unit.
• Memory may be implemented within the processor unit or external to the processor unit.
• the term "memory" refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.
• the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program.
• Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer.
• such computer- readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
• instructions and/or data may be provided as signals on transmission media included in a communication apparatus.
• a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

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• 2018
  • 2018-05-09 US US15/975,434 patent/US10559520B2/en active Active
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