JP7240148B2 - 光結合装置 - Google Patents
光結合装置 Download PDFInfo
- Publication number
- JP7240148B2 JP7240148B2 JP2018218229A JP2018218229A JP7240148B2 JP 7240148 B2 JP7240148 B2 JP 7240148B2 JP 2018218229 A JP2018218229 A JP 2018218229A JP 2018218229 A JP2018218229 A JP 2018218229A JP 7240148 B2 JP7240148 B2 JP 7240148B2
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- Prior art keywords
- lead
- mosfet
- semiconductor light
- region
- light receiving
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Description
図1(a)は第1の実施形態にかかる光結合装置の模式平面図、図1(b)はA-A線に沿った模式断面図、図1(c)はB-B線に沿った模式断面図、である。
光結合装置は、入力端子50と、出力端子53と、第1のMOSFET31と、第2のMOSFET32と、半導体受光素子20と、半導体発光素子10と、樹脂層90と、を有する。
透過する構成の材料の組み合わせとすることが小型化には望ましい。
図2(a)に表すように、透光性を有する基板11は、第1の面11aと、第1の面11aとは反対の側の第2の面11b、とを有する。第2の面11bに、発光層12(ドット線)を含む半導体積層体13が設けられる。半導体積層体13は、基板11の側とは反対の側の面に、表面から発光層12の下方まで到達する段差部を含む。段差部は、底面13aを有する。
半導体受光素子20は、制御回路28をさらに有することができる。制御回路28は、フォトダイオードアレイ20aの第1の電極26、29と、第2の電極23、27と、にそれぞれ接続されている。光信号がオンのとき、制御回路28は、フォトダイオードアレイ20aの電流や電圧をMOSFET31、32に供給する(たとえば、端子26,29と、端子23、27との間をオープンにする)。また、光信号がオフのとき、制御回路28は、MOSFET31、32のゲートGとソースSとの間を短絡し蓄積された電荷を引き抜き、MOSFET31、32をターンオフする(たとえば、第1の電極26、29と、第2の電極23、27との間をショートする)。
比較例にかかる光結合装置は、半導体受光素子120、半導体発光素子110、および第1および第2のMOSFET131、132が、実装部材上に配置されている。実装部材は、絶縁基板140、絶縁基板140の表面に設けられた入力端子150、ダイパッド161、162および絶縁基板140の表面に設けられた出力端子153を有している。
第1のMOSFET131のドレインと第3導電領域154との間、および第2のMOSFET132のドレインと第4導電領域155との間には、それぞれインダクタが接続される事になる。これらのインダクタは高域通過阻止フィルタとして作用し、高周波通過特性を低下させる。
本明細書において、光結合装置の高周波通過特性を、出力端子の第3リード54と出力端子の第4リード55との間または出力端子の第3導電領域154と出力端子の第4導電領域155との間の挿入損失(dB))で表すものとする。
比較例において、挿入損失が10dBとなる周波数は約16GHzである。これに対して、第1の実施形態では、挿入損失が10dBとなる周波数は、約19GHzと改善される。このため、高速パルスの波形歪が抑制され信号誤り率が低減される。すなわち、図6は、約13GHz以上において、出力端子で生じるインダクタンスが比較例の高周波通過特性を低下させることを示している。
光結合装置は、入力端子70と、出力端子73と、第1のMOSFET31と、第2のMOSFET32と、半導体受光素子20と、半導体発光素子10と、樹脂層90と、を有する。
光結合装置は、半導体受光素子220と、半導体発光素子230と、半導体制御素子272と、入力端子240と、出力端子250と、第1ダイパッド部221と、第2ダイパッド部222と、樹脂層260と、を有する。第1ダイパッド部221は吊ピン221a、第2ダイパッド部222は吊ピン222aをそれぞれ有する。なお、図8(a)は、樹脂層260(破線であらわす)を形成する前の平面図を表す。
Claims (6)
- 第1リードと、前記第1リードから離間した第2リードと、を含む入力端子と、
前記第1リードおよび前記第2リードから離間した第3リードおよび第4リードであって、それぞれ上面と下面と側面とを有する平板状の第3リードおよび第4リードを含み、前記第4リードは、前記第3リードから離間した、出力端子と、
第1の電極パッド領域および前記第1リードに隣接して配置された第1の接合領域を有する第1の面を有する第1のMOSFETであって、前記第3リードの前記上面に接合されることによりドレイン領域と前記第3リードとが電気的に接続された、第1のMOSFETと、
第2の電極パッド領域および前記第2リードに隣接して設けられた第2の接合領域を有する第1の面を有する第2のMOSFETであって、前記第4リードの前記上面に接合されることによりドレイン領域と前記第4リードとが電気的に接続され、前記第1のMOSFETから離間した第2のMOSFETと、
前記第1のMOSFETおよび前記第2のMOSFETの間のスペースを跨いで前記第1の接合領域および前記第2の接合領域に接合された半導体受光素子であって、前記第1および第2のMOSFETに接合された面とは反対側の面の中央部に設けられた受光領域と、前記受光領域の外側に設けられた電極パッド領域と、を有する、半導体受光素子と、
前記第1のMOSFETおよび前記第2のMOSFETの間の前記スペースの上方において、前記半導体受光素子の前記受光領域上に接続され、前記受光領域に向かって放出光を出射可能な半導体発光素子であって、前記入力端子に電気的に接続された半導体発光素子と、
前記第1および第2のMOSFET、前記半導体受光素子、前記半導体発光素子、前記第3リードおよび前記第4リードのそれぞれの前記上面および前記側面を封止し、前記第3リードおよび前記第4リードのそれぞれの前記下面を露出させる樹脂層と、
を備えた、光結合装置。 - 前記第1および第2のMOSFETはコモンソース接続とされ、かつ2つのソース電極は前記半導体受光素子の一方の電極にそれぞれ接続され、
前記第1および第2のMOSFETのゲート電極は、前記半導体受光素子の他方の電極にそれぞれ接続された、請求項1記載の光結合装置。 - 前記受光領域と前記半導体発光素子とを接着し、かつ透光性および絶縁性を有する接着層をさらに有する請求項1または2に記載の光結合装置。
- 前記入力端子の下面および前記出力端子の下面は、下方に向かって凸部となる段差を有する、請求項1~3のいずれか1つに記載の光結合装置。
- 前記入力端子の上面および前記出力端子の上面は、Agを含み、
前記入力端子の側面および前記出力端子の側面は、Cu、Ni、Pdのうちの少なくとも1つを含む、請求項1~4のいずれか1つに記載の光結合装置。 - 前記入力端子の上面および前記出力端子の上面は、酸化銀を含む請求項1~4のいずれか1つに記載の光結合装置。
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JP2008117962A (ja) | 2006-11-06 | 2008-05-22 | Yokogawa Electric Corp | 半導体リレー |
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US11688823B2 (en) | 2023-06-27 |
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