JP7237672B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7237672B2 JP7237672B2 JP2019049191A JP2019049191A JP7237672B2 JP 7237672 B2 JP7237672 B2 JP 7237672B2 JP 2019049191 A JP2019049191 A JP 2019049191A JP 2019049191 A JP2019049191 A JP 2019049191A JP 7237672 B2 JP7237672 B2 JP 7237672B2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
14 窒化シリコン層
16 酸化シリコン層
18 酸窒化シリコン層
22 下部配線層(第1の導電層)
24 上部配線層(第2の導電層)
26 ビアプラグ(第3の導電層)
28 下部コイル(第1のコイル)
30 上部コイル(第2のコイル)
100 アイソレータ(半導体装置)
IP 界面
θ1 第1の傾斜角
θ2 第2の傾斜角
Claims (5)
- 銅を含む第1の導電層と、
銅を含む第2の導電層と、
前記第1の導電層と、前記第2の導電層との間に設けられた窒化シリコン層と、
前記窒化シリコン層と前記第2の導電層との間に設けられ前記窒化シリコン層よりも厚い酸化シリコン層と、
前記酸化シリコン層と前記第2の導電層との間に設けられ、前記酸化シリコン層よりも厚い酸窒化シリコン層と、
前記第1の導電層と前記第2の導電層との間に設けられ、前記第1の導電層及び前記第2の導電層と電気的に接続された銅を含む第3の導電層と、
第1のコイルと、
第2のコイルと、を備え、
前記第1のコイルと前記第2のコイルとの間に、前記酸化シリコン層、及び、前記酸窒化シリコン層が設けられ、
前記第3の導電層が前記酸窒化シリコン層と接する面の前記窒化シリコン層と前記酸化シリコン層との界面に平行な面に対する第1の傾斜角が、前記第3の導電層が前記酸化シリコン層と接する面の前記界面に平行な面に対する第2の傾斜角よりも小さい半導体装置。 - 前記第1の導電層と前記第2の導電層との間の距離が6μm以上である請求項1記載の半導体装置。
- 前記第1の傾斜角は70度以上85度未満であり、前記第2の傾斜角は85度以上90度以下である請求項1又は請求項2記載の半導体装置。
- 前記第1の導電層と前記第3の導電層とが接する面の幅は6μm以上である請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記第1のコイルと前記第1の導電層は同一材料で形成され、前記第2のコイルと前記第1の導電層は同一材料で形成される請求項1ないし請求項4いずれか一項記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019049191A JP7237672B2 (ja) | 2019-03-15 | 2019-03-15 | 半導体装置 |
US16/556,335 US11183381B2 (en) | 2019-03-15 | 2019-08-30 | Semiconductor device |
Applications Claiming Priority (1)
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JP2019049191A JP7237672B2 (ja) | 2019-03-15 | 2019-03-15 | 半導体装置 |
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JP2020150241A JP2020150241A (ja) | 2020-09-17 |
JP7237672B2 true JP7237672B2 (ja) | 2023-03-13 |
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JP2019049191A Active JP7237672B2 (ja) | 2019-03-15 | 2019-03-15 | 半導体装置 |
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JP (1) | JP7237672B2 (ja) |
Families Citing this family (1)
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JP2022144836A (ja) * | 2021-03-19 | 2022-10-03 | 株式会社東芝 | アイソレータ |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010080774A (ja) | 2008-09-26 | 2010-04-08 | Rohm Co Ltd | 半導体装置 |
JP2014053369A (ja) | 2012-09-05 | 2014-03-20 | Toshiba Corp | 半導体装置およびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61207048A (ja) * | 1985-03-12 | 1986-09-13 | Seiko Instr & Electronics Ltd | 半導体装置 |
JPH08107106A (ja) | 1994-10-04 | 1996-04-23 | Sony Corp | コンタクトホール開口部のテーパ角度制御方法 |
JPH09283624A (ja) | 1996-04-18 | 1997-10-31 | Sony Corp | 半導体装置の製造方法 |
JPH11340322A (ja) * | 1998-05-21 | 1999-12-10 | Sony Corp | 半導体装置およびその製造方法 |
JP2006080244A (ja) | 2004-09-08 | 2006-03-23 | Sharp Corp | 半導体装置およびその製造方法 |
JP2007027291A (ja) | 2005-07-14 | 2007-02-01 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US10290532B2 (en) * | 2017-05-19 | 2019-05-14 | Analog Devices Global | Forming an isolation barrier in an isolator |
US10522468B2 (en) * | 2017-07-31 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
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2019
- 2019-03-15 JP JP2019049191A patent/JP7237672B2/ja active Active
- 2019-08-30 US US16/556,335 patent/US11183381B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010080774A (ja) | 2008-09-26 | 2010-04-08 | Rohm Co Ltd | 半導体装置 |
JP2014053369A (ja) | 2012-09-05 | 2014-03-20 | Toshiba Corp | 半導体装置およびその製造方法 |
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US20200294786A1 (en) | 2020-09-17 |
JP2020150241A (ja) | 2020-09-17 |
US11183381B2 (en) | 2021-11-23 |
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