JP7206728B2 - 半導体装置及び半導体装置の制御方法 - Google Patents
半導体装置及び半導体装置の制御方法 Download PDFInfo
- Publication number
- JP7206728B2 JP7206728B2 JP2018173583A JP2018173583A JP7206728B2 JP 7206728 B2 JP7206728 B2 JP 7206728B2 JP 2018173583 A JP2018173583 A JP 2018173583A JP 2018173583 A JP2018173583 A JP 2018173583A JP 7206728 B2 JP7206728 B2 JP 7206728B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- region
- circuit
- semiconductor element
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 183
- 238000000034 method Methods 0.000 title claims description 17
- 238000000605 extraction Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 21
- 230000010355 oscillation Effects 0.000 description 15
- 230000003071 parasitic effect Effects 0.000 description 15
- 238000001514 detection method Methods 0.000 description 10
- 230000002457 bidirectional effect Effects 0.000 description 9
- 108091006146 Channels Proteins 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 5
- 230000005856 abnormality Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000011144 upstream manufacturing Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
- H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Description
本発明の第1の実施形態に係る半導体装置は、図1に示すように、電力回路チップ3及び制御回路チップ5を備える。電力回路チップ3は、主スイッチ回路1及び温度センサ4を備える。主スイッチ回路1は、第1半導体素子2a及び第2半導体素子2bからなる双方向スイッチである。主スイッチ回路1は、第1及び第2半導体素子2a、2bのドレイン電極(第1及び第3主電極)を共通にして互いに逆向きに接続された双方向スイッチである。第1半導体素子2aのソース電極(第2主電極)が電源(VCC)接続用の電源ノード12に接続され、第2半導体素子2bのソース電極(第4主電極)が出力(OUT)用の出力ノード13に接続される。温度センサ4は、主スイッチ回路1の通電による温度変化を検知する。
図6は、第1の実施形態に係る半導体装置の構成例を示す平面図である。図6では、半導体装置の内部を示すために、樹脂パッケージ130を透視して示している。図6に示すように、第1の実施形態に係る半導体装置は、リードフレーム(111,112,113,114,115,116)、電力回路チップ3、制御回路チップ5、及び樹脂パッケージ130を備える。電力回路チップ3は、リードフレーム(111~116)に搭載される。制御回路チップ5は、電力回路チップ3に積層される。リードフレーム(111~116)は、ダイパッド111、及びリード端子112、113、114、115、116を有する。ダイパッド111には、電力回路チップ3のドレイン電極67が電気的に接続する。リード端子112、113、114、115、116のそれぞれには、電力回路チップ3や制御回路チップ5の各電極パッドが電気的に接続する。
多段昇圧部23aでは、1段目がインバータ24と、コンデンサ25と、2つのダイオード26,27とを有し、2段目がインバータ28と、コンデンサ29と、2つのダイオード30,31とを有している。
図10は、本発明の第2の実施形態に係る半導体装置の一例を説明する回路図である。図10に示すように、駆動回路6は、駆動信号が入力される処理回路16bと、処理回路16bに共通に電気的に接続された昇圧回路17c、17dを備える。また、出力回路7は、否定論理回路(インバータ)18cに共通に電気的に接続された電荷引抜半導体素子19c、19dを備える。第2の実施形態に係る半導体装置は、処理回路16bに共通に電気的に接続された昇圧回路17c、17d、及びインバータ18cに共通に電気的に接続された電荷引抜半導体素子19c、19dを備える点が第1の実施形態と異なる。他の構成は、第1の実施形態に係る半導体装置と同様であるので、重複した説明を省略する。
図11Aは、本発明の第2の実施形態に係る半導体装置の昇圧回路の構成例1を示す回路図であり、図11Bは、図11Aに示した昇圧回路17cの出力電圧の立ち上がりを示す図である。昇圧回路17dは、図9Aに示す昇圧回路17aと同じである。図11Aに示す昇圧回路17cは、昇圧回路17dに比べ多段昇圧部23bの段数が多く3段である。このように、昇圧回路17cの多段昇圧部の段数を昇圧回路17dより多くすることで、出力電圧の立ち上がりを速くすることができる。
図13Aは、本発明の第2の実施形態に係る半導体装置の昇圧回路の構成例2を示す回路図であり、図13Bは、図13Aに示した昇圧回路の出力電圧の立ち上がりを示す図である。昇圧回路17dは、図9Aに示す昇圧回路17aと同じである。図13Aに示す昇圧回路17cは、昇圧回路17dに比べ発振回路21aの周波数が高い。このように、昇圧回路17cの発振回路21aの周波数を昇圧回路17dの発振回路21の周波数より高くすることで、図13Bに示すように図9Aに示す昇圧回路17aよりも出力電圧の立ち上がりを速くすることができる。
図14Aは、本発明の第2の実施形態に係る半導体装置の昇圧回路の構成例3を示す回路図であり、図14Bは、図14Aに示した昇圧回路の出力電圧の立ち上がりを示す図である。昇圧回路17dは、図9Aに示す昇圧回路17aと同じである。図14Aに示す昇圧回路17cは、昇圧回路17dに比べコンデンサ25aの容量が大きい。このように、昇圧回路17cのコンデンサ25aの容量を昇圧回路17dのコンデンサ25の容量より大きくすることで、図14Bに示すように図9Aに示す昇圧回路17aよりも出力電圧の立ち上がりを速くすることができる。
上記のように、本発明を実施形態及び変形例によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。上記の実施形態の開示の趣旨を理解すれば、当業者には様々な代替実施形態、実施例及び運用技術が本発明に含まれ得ることが明らかとなろう。又、上記の実施形態及び各変形例において説明される各構成を任意に応用した構成等、本発明はここでは記載していない様々な実施形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の例示的説明から妥当な、特許請求の範囲に係る発明特定事項によってのみ定められるものである。
2a・・・第1半導体素子
2b・・・第2半導体素子
3・・・電力回路チップ
4・・・温度センサ
5・・・制御回路チップ
6・・・駆動回路
7・・・出力回路
8・・・過熱検出回路
9・・・論理回路
10・・・低電圧検出回路
11・・・内部電源
12・・・電源ノード
13・・・出力ノード
14・・・接地ノード
15・・・入力ノード
16・・・処理回路
17a、17b、17c、17d・・・昇圧回路
18a、18b、24、28、32・・・否定論理回路(インバータ)
19a、19b・・・電荷引抜半導体素子
20・・・負荷
22・・・外部電源
50・・・ドリフト領域
51・・・共通ドレイン領域(第1及び第3主電極領域)
52・・・半導体領域
53a、53b、54a、54b・・・ウェル領域
53a・・・第1のウェル領域
53b・・・第2のウェル領域
54a・・・第3のウェル領域
54b・・・第4のウェル領域
55・・・チャネルストッパ領域
56a、56b・・・コンタクト領域
57a・・・第1のソース領域(第2主電極領域)
57b・・・第2のソース領域(第4主電極領域)
58a、58b・・・素子分離膜
59a、59b・・・トレンチ
60a、60b・・・ゲート絶縁膜
61a、61b・・・ゲート電極(制御電極)
61A、61B・・・ゲート引出電極
61C・・・フィールドプレート電極
62a、62b・・・層間絶縁膜
63a、63b、63c、63d・・・ソースコンタクト層
64a、64b、64c、64d・・・ソース電極
65a、65b・・・ソース電極パッド
66a、66b・・・ゲート電極パッド
67・・・ドレイン電極
69・・・保護膜
112、113、114、115、116・・・リード端子
121、122、123、124、125、126・・・ボンディングワイヤ
130・・・樹脂パッケージ
Claims (8)
- 主スイッチ回路を構成するように第1導電型の半導体領域からなる共通領域を有し、該共通領域の上部に第2導電型の第1及び第2のウェル領域を互いに分離して設け、前記第1のウェル領域の上部に第1導電型の第1のソース領域を設けた第1半導体素子、及び前記第2のウェル領域の上部に第1導電型の第2のソース領域を設けた第2半導体素子と、
前記第1及び第2半導体素子の制御電極のそれぞれに互いに独立した第1駆動信号及び第2駆動信号を供給する駆動回路と、
を備え、
前記駆動回路は、前記第1及び第2半導体素子の前記制御電極のそれぞれに互いに独立して電気的に接続した第1及び第2昇圧回路と、前記第1及び第2昇圧回路のそれぞれが互いに独立して電気的に接続された処理回路とを有し、
前記第1半導体素子の前記制御電極に接続された前記第1昇圧回路の出力電圧のレベルが、前記第2半導体素子の前記制御電極に接続された前記第2昇圧回路の出力電圧よりも高いことを特徴とする半導体装置。 - 前記第1及び第2半導体素子のそれぞれは、
前記第1及び第2のウェル領域の上部に設けられた第2導電型のコンタクト領域と、 を更に備え、
前記第1半導体素子の前記コンタクト領域が、電源端子に電気的に接続され、前記第2半導体素子の前記コンタクト領域が、出力端子に電気的に接続されることを特徴とする請求項1に記載の半導体装置。 - 前記半導体領域は、
第1半導体領域と、
前記第1半導体領域と接し、前記第1及び第2のウェル領域と距離を有し、前記第1半導体領域よりも不純物濃度が高い第2半導体領域と、を有することを特徴とする請求項1に記載の半導体装置。 - 前記第1半導体領域は、前記第1及び第2のウェル領域を備える第1半導体層であり、
前記第2半導体領域は、前記第1半導体層の下に形成された第2半導体層であることを特徴とする請求項3に記載の半導体装置。 - 入力のそれぞれが前記第1及び第2昇圧回路のそれぞれの入力側に電気的に接続された否定論理回路、制御電極のそれぞれが前記否定論理回路のそれぞれの出力に電気的に接続され、前記第1及び第2昇圧回路それぞれと前記出力端子とに、第1主電極領域及び他方の電極領域がそれぞれ電気的に接続された電荷引抜半導体素子を有する出力回路を更に備えることを特徴とする請求項2に記載の半導体装置。
- 前記第1半導体素子の前記制御電極に接続された前記第1昇圧回路の出力電圧の立ち上がりが、前記第2半導体素子の前記制御電極に接続された前記第2昇圧回路の出力電圧の立ち上がりよりも早いことを特徴とする請求項1~5のいずれか1項に記載の半導体装置。
- 前記第1及び第2半導体素子を同一チップ上に集積化した電力回路チップ、前記駆動回路を同一チップ上に集積化した制御回路チップ、前記電力回路チップ及び前記制御回路チップを内蔵し、前記共通領域を電気的に外部に引き出し、外部電源に接続可能な電源端子、前記第2のソース領域を電気的に外部に引き出し、外部の負荷に接続可能な出力端子を有するパッケージを備えることを特徴とする請求項1に記載の半導体装置。
- 共通領域となる第1導電型の半導体領域を有し、前記共通領域の上部に第2導電型の第1及び第2のウェル領域を互いに分離して設け、前記第1のウェル領域の上部に設けた第1導電型の第2主電極領域の上面に、電源端子に電気的に接続された第1表面電極を設けた絶縁ゲート型の第1半導体素子、及び前記第2のウェル領域の上部に設けた第4主電極領域の上面に、出力端子に電気的に接続された第2表面電極を設けた絶縁ゲート型の第2半導体素子を有する主スイッチ回路を有し、
前記第1半導体素子の制御電極に第1駆動信号を印加し、前記第1半導体素子の導通及び遮断を制御し、
前記第2半導体素子の制御電極に、前記第1駆動信号とは独立して第2駆動信号を印加し、前記第2半導体素子の導通及び遮断を制御する
ことを含み、
前記第1半導体素子が導通状態の間に、前記第2駆動信号の導通及び遮断の切替を行い、
前記第1及び第2駆動信号のそれぞれが、互いに独立した昇圧回路を介して前記第1及び第2半導体素子のそれぞれの前記制御電極に印加され、
前記第1半導体素子を導通状態にする前記第1駆動信号の電圧レベルが、前記第2半導体素子を導通状態にする前記第2駆動信号の電圧レベルより高いことを特徴とする半導体装置の制御方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018173583A JP7206728B2 (ja) | 2018-09-18 | 2018-09-18 | 半導体装置及び半導体装置の制御方法 |
US16/521,007 US10868530B2 (en) | 2018-09-18 | 2019-07-24 | Semiconductor device and method for controlling semiconductor device |
CN201910705940.3A CN110911399A (zh) | 2018-09-18 | 2019-08-01 | 半导体装置以及半导体装置的控制方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018173583A JP7206728B2 (ja) | 2018-09-18 | 2018-09-18 | 半導体装置及び半導体装置の制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020047705A JP2020047705A (ja) | 2020-03-26 |
JP7206728B2 true JP7206728B2 (ja) | 2023-01-18 |
Family
ID=69773342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018173583A Active JP7206728B2 (ja) | 2018-09-18 | 2018-09-18 | 半導体装置及び半導体装置の制御方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10868530B2 (ja) |
JP (1) | JP7206728B2 (ja) |
CN (1) | CN110911399A (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7002423B2 (ja) * | 2018-08-24 | 2022-01-20 | 株式会社東芝 | スイッチ回路 |
US10917082B1 (en) * | 2020-02-04 | 2021-02-09 | Infineon Technologies Americas Corp. | Power module and electronic system |
JP2023106740A (ja) * | 2022-01-21 | 2023-08-02 | 株式会社東芝 | 駆動装置及び半導体モジュール |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004274039A (ja) | 2003-02-17 | 2004-09-30 | Fuji Electric Device Technology Co Ltd | 双方向素子およびその製造方法、半導体装置 |
JP2008010813A (ja) | 2006-05-29 | 2008-01-17 | Fuji Electric Device Technology Co Ltd | 半導体装置、バッテリー保護回路およびバッテリーパック |
JP4178331B2 (ja) | 1998-03-02 | 2008-11-12 | 株式会社安川電機 | 直列多重パルス幅変調サイクロコンバータ装置およびその制御方法 |
JP2010166301A (ja) | 2009-01-15 | 2010-07-29 | Daikin Ind Ltd | スイッチ回路 |
JP2012119577A (ja) | 2010-12-02 | 2012-06-21 | Renesas Electronics Corp | 半導体チップ、半導体装置、及び半導体チップの製造方法 |
JP2017028213A (ja) | 2015-07-28 | 2017-02-02 | 新電元工業株式会社 | 半導体リレー素子及び半導体リレーモジュール |
JP2017139790A (ja) | 2017-03-23 | 2017-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4178831B2 (ja) | 2002-05-13 | 2008-11-12 | 株式会社三洋物産 | 遊技機 |
JP2009088006A (ja) | 2007-09-27 | 2009-04-23 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置 |
JP2011151120A (ja) * | 2010-01-20 | 2011-08-04 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP5990437B2 (ja) | 2012-09-10 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US8841940B2 (en) * | 2013-02-06 | 2014-09-23 | Infineon Technologies Austria Ag | System and method for a driver circuit |
JP6379778B2 (ja) | 2014-07-15 | 2018-08-29 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
DE102016112162A1 (de) * | 2016-07-04 | 2018-01-04 | Infineon Technologies Ag | Elektronische schalt- und verpolschutzschaltung |
JP6722101B2 (ja) | 2016-12-27 | 2020-07-15 | ルネサスエレクトロニクス株式会社 | 半導体装置および過電流保護装置 |
-
2018
- 2018-09-18 JP JP2018173583A patent/JP7206728B2/ja active Active
-
2019
- 2019-07-24 US US16/521,007 patent/US10868530B2/en active Active
- 2019-08-01 CN CN201910705940.3A patent/CN110911399A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4178331B2 (ja) | 1998-03-02 | 2008-11-12 | 株式会社安川電機 | 直列多重パルス幅変調サイクロコンバータ装置およびその制御方法 |
JP2004274039A (ja) | 2003-02-17 | 2004-09-30 | Fuji Electric Device Technology Co Ltd | 双方向素子およびその製造方法、半導体装置 |
JP2008010813A (ja) | 2006-05-29 | 2008-01-17 | Fuji Electric Device Technology Co Ltd | 半導体装置、バッテリー保護回路およびバッテリーパック |
JP2010166301A (ja) | 2009-01-15 | 2010-07-29 | Daikin Ind Ltd | スイッチ回路 |
JP2012119577A (ja) | 2010-12-02 | 2012-06-21 | Renesas Electronics Corp | 半導体チップ、半導体装置、及び半導体チップの製造方法 |
JP2017028213A (ja) | 2015-07-28 | 2017-02-02 | 新電元工業株式会社 | 半導体リレー素子及び半導体リレーモジュール |
JP2017139790A (ja) | 2017-03-23 | 2017-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US10868530B2 (en) | 2020-12-15 |
CN110911399A (zh) | 2020-03-24 |
US20200091911A1 (en) | 2020-03-19 |
JP2020047705A (ja) | 2020-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9048119B2 (en) | Semiconductor device with normally off and normally on transistors | |
US7122875B2 (en) | Semiconductor device | |
JP5503897B2 (ja) | 半導体装置 | |
JP5991435B2 (ja) | 半導体装置 | |
JP4577425B2 (ja) | 半導体装置 | |
JP7206728B2 (ja) | 半導体装置及び半導体装置の制御方法 | |
JP6008054B2 (ja) | 半導体装置 | |
US11398818B2 (en) | Semiconductor device | |
US20210143148A1 (en) | Semiconductor device | |
US20150021711A1 (en) | Semiconductor device | |
US20150318392A1 (en) | Semiconductor device | |
JP7043825B2 (ja) | 半導体集積回路 | |
US9893065B2 (en) | Semiconductor integrated circuit | |
JP2009206284A (ja) | 半導体装置 | |
JP2017174858A (ja) | 半導体装置 | |
US20160226486A1 (en) | Semiconductor device and semiconductor relay using same | |
CN111030431A (zh) | 半导体装置 | |
US10217765B2 (en) | Semiconductor integrated circuit | |
US20210013203A1 (en) | Method of manufacturing semiconductor integrated circuit | |
US10727228B2 (en) | Stacked integrated circuit | |
JP6370952B2 (ja) | 半導体装置 | |
US20230187437A1 (en) | Semiconductor device | |
CN114843259A (zh) | 半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210811 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220630 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220705 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220819 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20221206 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20221219 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7206728 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |