JP7173751B2 - メモリモジュール、メモリシステム及び動作方法 - Google Patents

メモリモジュール、メモリシステム及び動作方法 Download PDF

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Publication number
JP7173751B2
JP7173751B2 JP2018078994A JP2018078994A JP7173751B2 JP 7173751 B2 JP7173751 B2 JP 7173751B2 JP 2018078994 A JP2018078994 A JP 2018078994A JP 2018078994 A JP2018078994 A JP 2018078994A JP 7173751 B2 JP7173751 B2 JP 7173751B2
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internal
data
memory module
nvdimm
termination
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Japanese (ja)
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JP2018190401A5 (enExample
JP2018190401A (ja
Inventor
▲そん▼ ▲よん▼ 林
熙 鐘 申
仁 壽 崔
榮 鎬 李
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020170102574A external-priority patent/KR102400102B1/ko
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Publication of JP2018190401A5 publication Critical patent/JP2018190401A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2018078994A 2017-05-11 2018-04-17 メモリモジュール、メモリシステム及び動作方法 Active JP7173751B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2017-0058904 2017-05-11
KR20170058904 2017-05-11
KR10-2017-0102574 2017-08-11
KR1020170102574A KR102400102B1 (ko) 2017-05-11 2017-08-11 데이터 버퍼의 내부 데이터(dq) 터미네이션을 지원하는 메모리 시스템

Publications (3)

Publication Number Publication Date
JP2018190401A JP2018190401A (ja) 2018-11-29
JP2018190401A5 JP2018190401A5 (enExample) 2021-05-13
JP7173751B2 true JP7173751B2 (ja) 2022-11-16

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JP2018078994A Active JP7173751B2 (ja) 2017-05-11 2018-04-17 メモリモジュール、メモリシステム及び動作方法

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US (2) US10496584B2 (enExample)
JP (1) JP7173751B2 (enExample)
CN (1) CN108874306B (enExample)
DE (1) DE102018106863A1 (enExample)

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US11500576B2 (en) 2017-08-26 2022-11-15 Entrantech Inc. Apparatus and architecture of non-volatile memory module in parallel configuration
US10831963B1 (en) * 2017-08-26 2020-11-10 Kong-Chen Chen Apparatus and method of parallel architecture for NVDIMM
US11537521B2 (en) * 2019-06-05 2022-12-27 Samsung Electronics Co., Ltd. Non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM
CN120469946A (zh) * 2019-11-15 2025-08-12 安徽寒武纪信息科技有限公司 一种存储器以及包括该存储器的设备
CN111045955B (zh) * 2019-12-16 2023-09-22 瓴盛科技有限公司 架构动态配置的存储装置及其操作方法及电子设备
CN113360430B (zh) * 2021-06-22 2022-09-09 中国科学技术大学 动态随机存取存储器系统通信架构
US20250245145A1 (en) * 2024-01-29 2025-07-31 Western Digital Technologies, Inc. Non-target on-die termination

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JP2003068082A (ja) 2001-08-24 2003-03-07 Elpida Memory Inc メモリデバイス及びメモリシステム
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KR20060031109A (ko) 2004-10-07 2006-04-12 삼성전자주식회사 멀티 랭크 메모리 시스템 및 이를 위한 메모리 랭크별 온다이 터미네이션 저항 조절 방법
US7479799B2 (en) 2006-03-14 2009-01-20 Inphi Corporation Output buffer with switchable output impedance
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KR101841622B1 (ko) * 2010-11-04 2018-05-04 삼성전자주식회사 온-다이 터미네이션 회로를 가지는 불휘발성 메모리 장치 및 그것의 제어 방법
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KR102219451B1 (ko) * 2014-09-22 2021-02-24 삼성전자주식회사 스토리지 컨트롤러, 이의 동작 방법 및 이를 포함하는 솔리드 스테이트 디스크
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Patent Citations (3)

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JP2001357684A (ja) 2000-06-12 2001-12-26 Sharp Corp 半導体記憶装置
JP2003068082A (ja) 2001-08-24 2003-03-07 Elpida Memory Inc メモリデバイス及びメモリシステム
US20130254497A1 (en) 2007-06-01 2013-09-26 Netlist, Inc. Isolation switching for backup of registered memory

Also Published As

Publication number Publication date
US10684979B2 (en) 2020-06-16
US20180329850A1 (en) 2018-11-15
DE102018106863A1 (de) 2018-11-15
JP2018190401A (ja) 2018-11-29
CN108874306B (zh) 2022-08-16
US20200065289A1 (en) 2020-02-27
CN108874306A (zh) 2018-11-23
US10496584B2 (en) 2019-12-03

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