JP2018190401A5 - - Google Patents

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JP2018190401A5
JP2018190401A5 JP2018078994A JP2018078994A JP2018190401A5 JP 2018190401 A5 JP2018190401 A5 JP 2018190401A5 JP 2018078994 A JP2018078994 A JP 2018078994A JP 2018078994 A JP2018078994 A JP 2018078994A JP 2018190401 A5 JP2018190401 A5 JP 2018190401A5
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Japan
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internal
nvdimm
data
termination
operating mode
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JP2018078994A
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Japanese (ja)
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JP2018190401A (ja
JP7173751B2 (ja
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Priority claimed from KR1020170102574A external-priority patent/KR102400102B1/ko
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JP2018078994A 2017-05-11 2018-04-17 メモリモジュール、メモリシステム及び動作方法 Active JP7173751B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2017-0058904 2017-05-11
KR20170058904 2017-05-11
KR10-2017-0102574 2017-08-11
KR1020170102574A KR102400102B1 (ko) 2017-05-11 2017-08-11 데이터 버퍼의 내부 데이터(dq) 터미네이션을 지원하는 메모리 시스템

Publications (3)

Publication Number Publication Date
JP2018190401A JP2018190401A (ja) 2018-11-29
JP2018190401A5 true JP2018190401A5 (enExample) 2021-05-13
JP7173751B2 JP7173751B2 (ja) 2022-11-16

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JP2018078994A Active JP7173751B2 (ja) 2017-05-11 2018-04-17 メモリモジュール、メモリシステム及び動作方法

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US (2) US10496584B2 (enExample)
JP (1) JP7173751B2 (enExample)
CN (1) CN108874306B (enExample)
DE (1) DE102018106863A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11500576B2 (en) 2017-08-26 2022-11-15 Entrantech Inc. Apparatus and architecture of non-volatile memory module in parallel configuration
US10831963B1 (en) * 2017-08-26 2020-11-10 Kong-Chen Chen Apparatus and method of parallel architecture for NVDIMM
US11537521B2 (en) * 2019-06-05 2022-12-27 Samsung Electronics Co., Ltd. Non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM
CN120469946A (zh) * 2019-11-15 2025-08-12 安徽寒武纪信息科技有限公司 一种存储器以及包括该存储器的设备
CN111045955B (zh) * 2019-12-16 2023-09-22 瓴盛科技有限公司 架构动态配置的存储装置及其操作方法及电子设备
CN113360430B (zh) * 2021-06-22 2022-09-09 中国科学技术大学 动态随机存取存储器系统通信架构
US20250245145A1 (en) * 2024-01-29 2025-07-31 Western Digital Technologies, Inc. Non-target on-die termination

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KR20060031109A (ko) 2004-10-07 2006-04-12 삼성전자주식회사 멀티 랭크 메모리 시스템 및 이를 위한 메모리 랭크별 온다이 터미네이션 저항 조절 방법
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