CN108874306B - 用于支持数据缓冲器的内部dq终结的存储器系统 - Google Patents
用于支持数据缓冲器的内部dq终结的存储器系统 Download PDFInfo
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- CN108874306B CN108874306B CN201810329996.9A CN201810329996A CN108874306B CN 108874306 B CN108874306 B CN 108874306B CN 201810329996 A CN201810329996 A CN 201810329996A CN 108874306 B CN108874306 B CN 108874306B
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- memory module
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2017-0058904 | 2017-05-11 | ||
| KR20170058904 | 2017-05-11 | ||
| KR10-2017-0102574 | 2017-08-11 | ||
| KR1020170102574A KR102400102B1 (ko) | 2017-05-11 | 2017-08-11 | 데이터 버퍼의 내부 데이터(dq) 터미네이션을 지원하는 메모리 시스템 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108874306A CN108874306A (zh) | 2018-11-23 |
| CN108874306B true CN108874306B (zh) | 2022-08-16 |
Family
ID=63962703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810329996.9A Active CN108874306B (zh) | 2017-05-11 | 2018-04-13 | 用于支持数据缓冲器的内部dq终结的存储器系统 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US10496584B2 (enExample) |
| JP (1) | JP7173751B2 (enExample) |
| CN (1) | CN108874306B (enExample) |
| DE (1) | DE102018106863A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11500576B2 (en) | 2017-08-26 | 2022-11-15 | Entrantech Inc. | Apparatus and architecture of non-volatile memory module in parallel configuration |
| US10831963B1 (en) * | 2017-08-26 | 2020-11-10 | Kong-Chen Chen | Apparatus and method of parallel architecture for NVDIMM |
| US11537521B2 (en) * | 2019-06-05 | 2022-12-27 | Samsung Electronics Co., Ltd. | Non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM |
| CN120469946A (zh) * | 2019-11-15 | 2025-08-12 | 安徽寒武纪信息科技有限公司 | 一种存储器以及包括该存储器的设备 |
| CN111045955B (zh) * | 2019-12-16 | 2023-09-22 | 瓴盛科技有限公司 | 架构动态配置的存储装置及其操作方法及电子设备 |
| CN113360430B (zh) * | 2021-06-22 | 2022-09-09 | 中国科学技术大学 | 动态随机存取存储器系统通信架构 |
| US20250245145A1 (en) * | 2024-01-29 | 2025-07-31 | Western Digital Technologies, Inc. | Non-target on-die termination |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890688A (zh) * | 2011-07-28 | 2014-06-25 | 奈特力斯公司 | 一种flash-dram混合存储器模块 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3871184B2 (ja) | 2000-06-12 | 2007-01-24 | シャープ株式会社 | 半導体記憶装置 |
| JP3799251B2 (ja) | 2001-08-24 | 2006-07-19 | エルピーダメモリ株式会社 | メモリデバイス及びメモリシステム |
| KR100606242B1 (ko) * | 2004-01-30 | 2006-07-31 | 삼성전자주식회사 | 불휘발성 메모리와 호스트간에 버퍼링 동작을 수행하는멀티 포트 휘발성 메모리 장치, 이를 이용한 멀티-칩패키지 반도체 장치 및 이를 이용한 데이터 처리장치 |
| KR20060031109A (ko) | 2004-10-07 | 2006-04-12 | 삼성전자주식회사 | 멀티 랭크 메모리 시스템 및 이를 위한 메모리 랭크별 온다이 터미네이션 저항 조절 방법 |
| US7479799B2 (en) | 2006-03-14 | 2009-01-20 | Inphi Corporation | Output buffer with switchable output impedance |
| US7486104B2 (en) | 2006-06-02 | 2009-02-03 | Rambus Inc. | Integrated circuit with graduated on-die termination |
| US7716411B2 (en) * | 2006-06-07 | 2010-05-11 | Microsoft Corporation | Hybrid memory device with single interface |
| KR100790821B1 (ko) * | 2006-11-15 | 2008-01-03 | 삼성전자주식회사 | 반도체 메모리 장치에서의 온다이 터미네이션 회로 |
| US8301833B1 (en) * | 2007-06-01 | 2012-10-30 | Netlist, Inc. | Non-volatile memory module |
| US7818497B2 (en) | 2007-08-31 | 2010-10-19 | International Business Machines Corporation | Buffered memory module supporting two independent memory channels |
| DE202010017690U1 (de) * | 2009-06-09 | 2012-05-29 | Google, Inc. | Programmierung von Dimm-Abschlusswiderstandswerten |
| US8539145B1 (en) * | 2009-07-28 | 2013-09-17 | Hewlett-Packard Development Company, L.P. | Increasing the number of ranks per channel |
| US8274308B2 (en) | 2010-06-28 | 2012-09-25 | Intel Corporation | Method and apparatus for dynamic memory termination |
| US9153296B2 (en) | 2010-06-28 | 2015-10-06 | Intel Corporation | Methods and apparatuses for dynamic memory termination |
| KR101841622B1 (ko) * | 2010-11-04 | 2018-05-04 | 삼성전자주식회사 | 온-다이 터미네이션 회로를 가지는 불휘발성 메모리 장치 및 그것의 제어 방법 |
| US9158726B2 (en) * | 2011-12-16 | 2015-10-13 | Inphi Corporation | Self terminated dynamic random access memory |
| US9747230B2 (en) | 2012-10-15 | 2017-08-29 | Rambus Inc. | Memory rank and ODT configuration in a memory system |
| US8923065B2 (en) | 2012-12-31 | 2014-12-30 | SanDisk Technologies, Inc. | Nonvolatile memory and method with improved I/O interface |
| US9858181B2 (en) * | 2013-06-20 | 2018-01-02 | Hitachi, Ltd. | Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein |
| CN105684086A (zh) * | 2013-09-27 | 2016-06-15 | 慧与发展有限责任合伙企业 | 存储器模块上的存储器备用 |
| US20150261446A1 (en) | 2014-03-12 | 2015-09-17 | Futurewei Technologies, Inc. | Ddr4-onfi ssd 1-to-n bus adaptation and expansion controller |
| KR102219451B1 (ko) * | 2014-09-22 | 2021-02-24 | 삼성전자주식회사 | 스토리지 컨트롤러, 이의 동작 방법 및 이를 포함하는 솔리드 스테이트 디스크 |
| US10613995B2 (en) | 2015-03-16 | 2020-04-07 | Rambus Inc. | Training and operations with a double buffered memory topology |
| US10255220B2 (en) | 2015-03-30 | 2019-04-09 | Rambus Inc. | Dynamic termination scheme for memory communication |
| US10141935B2 (en) | 2015-09-25 | 2018-11-27 | Intel Corporation | Programmable on-die termination timing in a multi-rank system |
| KR20170075103A (ko) * | 2015-12-22 | 2017-07-03 | 삼성전자주식회사 | 온 다이 터미네이션 회로를 포함하는 메모리 모듈 및 그것의 온 다이 터미네이션 제어 방법 |
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2018
- 2018-03-09 US US15/916,929 patent/US10496584B2/en active Active
- 2018-03-22 DE DE102018106863.8A patent/DE102018106863A1/de active Pending
- 2018-04-13 CN CN201810329996.9A patent/CN108874306B/zh active Active
- 2018-04-17 JP JP2018078994A patent/JP7173751B2/ja active Active
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2019
- 2019-11-01 US US16/671,601 patent/US10684979B2/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890688A (zh) * | 2011-07-28 | 2014-06-25 | 奈特力斯公司 | 一种flash-dram混合存储器模块 |
Also Published As
| Publication number | Publication date |
|---|---|
| US10684979B2 (en) | 2020-06-16 |
| US20180329850A1 (en) | 2018-11-15 |
| DE102018106863A1 (de) | 2018-11-15 |
| JP2018190401A (ja) | 2018-11-29 |
| JP7173751B2 (ja) | 2022-11-16 |
| US20200065289A1 (en) | 2020-02-27 |
| CN108874306A (zh) | 2018-11-23 |
| US10496584B2 (en) | 2019-12-03 |
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