JP7145313B2 - 半導体デバイス及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000010410 layer Substances 0.000 claims description 118
- 238000002955 isolation Methods 0.000 claims description 106
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- -1 nitrogen containing compound Chemical class 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000779 depleting effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (13)
- ドリフト領域と、
上記ドリフト領域に接しており、第1アイソレーション層、その第1アイソレーション層上に形成された孔エッチング停止層、並びにその孔エッチング停止層上に形成された第2アイソレーション層を備えるアイソレーション構造と、
上記孔エッチング停止層の上方に配置されその孔エッチング停止層に接している孔フィールドプレートと、
ポリシリコンゲート及びポリシリコンフィールドプレートが備わるポリシリコン構造と、を備え、
上記孔フィールドプレートは、上記ポリシリコン構造と直接接触しておらず、
上記第1アイソレーション層の厚さは、半導体デバイスに要求される耐圧に応じて設定されている、
半導体デバイス。 - 請求項1に係る半導体デバイスであって、上記アイソレーション構造がシャロウトレンチアイソレーション構造であり、上記第1アイソレーション層及び上記第2アイソレーション層が酸化シリコンで作成されている半導体デバイス。
- 請求項2に係る半導体デバイスであって、上記孔エッチング停止層が窒素含有化合物で作成されている半導体デバイス。
- 請求項1に係る半導体デバイスであって、更に金属層を備え、上記孔フィールドプレートの頂部がその金属層に接続されている半導体デバイス。
- 請求項4に係る半導体デバイスであって、更に、上記アイソレーション構造・上記金属層間に配置された層間誘電体を備え、上記孔フィールドプレートがその層間誘電体を縦貫して延びそれら金属層及びアイソレーション構造を接続している半導体デバイス。
- 請求項1に係る半導体デバイスであって、横拡散金属酸化物半導体電界効果トランジスタである半導体デバイス。
- 請求項6に係る半導体デバイスであって、更にドレイン領域及びソース領域を備え、上記ポリシリコンゲートがドレイン領域・ソース領域間領域の上方に所在しており、そのドレイン領域が上記ドリフト領域内に所在しており、そのドレイン領域が上記アイソレーション構造からみて当該ポリシリコンゲートとは逆側に所在している半導体デバイス。
- 請求項7に係る半導体デバイスであって、更に、第2導電型の基板と、その基板内に形成された第2導電型のウェル領域と、を備え、上記ポリシリコンゲートから見て上記アイソレーション構造とは逆の側が当該第2導電型のウェル領域上まで延びており、上記ドリフト領域が第1導電型であり、そのドリフト領域が当該基板内に所在している半導体デバイス。
- 請求項8に係る半導体デバイスであって、更に、第2導電型の上記ウェル領域内に所在する第2導電型のドープト領域を備え、その第2導電型のドープト領域が、上記ソース領域を挟み上記ポリシリコンゲートから離れた側に所在している半導体デバイス。
- 請求項8に係る半導体デバイスであって、第1導電型がN型、第2導電型がP型である半導体デバイス。
- 半導体デバイスを製造する方法であって、
基板の表面上にトレンチを形成し、
そのトレンチの内表面上に第1アイソレーション層を形成し、
その第1アイソレーション層上に孔エッチング停止層を形成し、
上記トレンチ内の残余領域に第2アイソレーション層を形成し、
これら第1アイソレーション層、孔エッチング停止層及び第2アイソレーション層が備わるアイソレーション構造と接するドリフト領域を形成し、
上記第2アイソレーション層を貫き上記孔エッチング停止層まで延びるフィールドプレート孔をエッチングによって形成し、
上記フィールドプレート孔内に素材を充填することで孔フィールドプレートを形成し、
ポリシリコンを堆積して、ポリシリコンゲート及びポリシリコンフィールドプレートを含むポリシリコン構造を形成し、
上記フィールドプレート孔は、上記ポリシリコン構造と直接接触しておらず、
上記第1アイソレーション層の厚さは、半導体デバイスに必要な耐圧に応じて設定される、方法。 - 請求項11に係る方法であって、更に、上記アイソレーション構造上に層間誘電体を形成する工程を有し、上記フィールドプレート孔をエッチングによって形成する上掲の工程にて、その層間誘電体を縦貫するエッチングの後に、続いて上記第2アイソレーション層を下方に向かい上記孔エッチング停止層までエッチングする方法。
- 請求項11に係る方法であって、上記トレンチの内表面上に上記第1アイソレーション層を形成する上掲の工程にて、酸化シリコンを熱成長させる方法。
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CN201810840983.8 | 2018-07-27 | ||
CN201810840983.8A CN110767740B (zh) | 2018-07-27 | 2018-07-27 | 半导体器件及其制造方法 |
PCT/CN2019/097836 WO2020020328A1 (zh) | 2018-07-27 | 2019-07-26 | 半导体器件及其制造方法 |
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US (1) | US11588049B2 (ja) |
EP (1) | EP3832733A4 (ja) |
JP (1) | JP7145313B2 (ja) |
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CN114335163A (zh) * | 2020-09-30 | 2022-04-12 | 芯恩(青岛)集成电路有限公司 | 具有垂直浮空场板的ldmos晶体管及其制备方法 |
CN115206802A (zh) * | 2021-04-12 | 2022-10-18 | 联华电子股份有限公司 | 横向扩散金属氧化物半导体元件及其制作方法 |
TWI792495B (zh) * | 2021-08-16 | 2023-02-11 | 立錡科技股份有限公司 | 功率元件及其製造方法 |
CN116978788A (zh) * | 2023-09-25 | 2023-10-31 | 粤芯半导体技术股份有限公司 | 多层场板结构的ldmos器件及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003332424A (ja) | 2002-05-14 | 2003-11-21 | Sharp Corp | 半導体装置の製造方法 |
WO2010013683A1 (ja) | 2008-08-01 | 2010-02-04 | 日本電気株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2011171638A (ja) | 2010-02-22 | 2011-09-01 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2015162581A (ja) | 2014-02-27 | 2015-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017028116A (ja) | 2015-07-23 | 2017-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07135249A (ja) * | 1993-11-09 | 1995-05-23 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
TW466747B (en) * | 2000-12-14 | 2001-12-01 | United Microelectronics Corp | Using inner field ring and complex multiple field plates to reduce surface breakdown of power LDMOSFET |
US7118987B2 (en) * | 2004-01-29 | 2006-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of achieving improved STI gap fill with reduced stress |
JP2005303253A (ja) * | 2004-03-18 | 2005-10-27 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
US8134208B2 (en) * | 2007-09-26 | 2012-03-13 | Globalfoundries Inc. | Semiconductor device having decreased contact resistance |
US7956412B2 (en) * | 2007-12-04 | 2011-06-07 | International Business Machines Corporation | Lateral diffusion field effect transistor with a trench field plate |
JP4602465B2 (ja) * | 2008-12-04 | 2010-12-22 | 株式会社東芝 | 半導体装置 |
US20110115018A1 (en) * | 2009-11-13 | 2011-05-19 | Maxim Integrated Products, Inc. | Mos power transistor |
US8981475B2 (en) | 2013-06-18 | 2015-03-17 | International Business Machines Corporation | Lateral diffusion metal oxide semiconductor (LDMOS) |
DE102014206361A1 (de) * | 2014-04-03 | 2015-10-08 | Robert Bosch Gmbh | Verfahren zur Herstellung einer dielektrischen Feldplatte in einem Graben eines Substrats, nach dem Verfahren erhältliches Substrat und Leistungstransistor mit einem solchen Substrat |
US9842903B2 (en) * | 2014-10-20 | 2017-12-12 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same |
CN104538309A (zh) | 2014-12-31 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | 低导通电阻ldmos 的结构及制作方法 |
CN104992977B (zh) * | 2015-05-25 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | Nldmos器件及其制造方法 |
DE102015112427B4 (de) | 2015-07-29 | 2017-04-06 | Infineon Technologies Ag | Halbleitervorrichtung mit einer allmählich zunehmenden Felddielektrikumsschicht und Verfahren zum Herstellen einer Halbleitervorrichtung |
CN106549052B (zh) * | 2015-09-17 | 2021-05-25 | 联华电子股份有限公司 | 横向扩散金属氧化物半导体晶体管及其制作方法 |
KR102286013B1 (ko) * | 2015-10-07 | 2021-08-05 | 에스케이하이닉스 시스템아이씨 주식회사 | 트랜치 절연 필드플레이트 및 금속 필드플레이트를 갖는 수평형 고전압 집적소자 |
US10804389B2 (en) * | 2016-02-25 | 2020-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | LDMOS transistor |
US11411086B2 (en) * | 2020-03-17 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field plate and isolation structure for high voltage device |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003332424A (ja) | 2002-05-14 | 2003-11-21 | Sharp Corp | 半導体装置の製造方法 |
WO2010013683A1 (ja) | 2008-08-01 | 2010-02-04 | 日本電気株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2011171638A (ja) | 2010-02-22 | 2011-09-01 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2015162581A (ja) | 2014-02-27 | 2015-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017028116A (ja) | 2015-07-23 | 2017-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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US20210234041A1 (en) | 2021-07-29 |
EP3832733A1 (en) | 2021-06-09 |
EP3832733A4 (en) | 2022-04-20 |
KR20210034650A (ko) | 2021-03-30 |
JP2021532594A (ja) | 2021-11-25 |
US11588049B2 (en) | 2023-02-21 |
KR102520058B1 (ko) | 2023-04-10 |
WO2020020328A1 (zh) | 2020-01-30 |
CN110767740B (zh) | 2021-10-15 |
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