CN104538309A - 低导通电阻ldmos 的结构及制作方法 - Google Patents

低导通电阻ldmos 的结构及制作方法 Download PDF

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CN104538309A
CN104538309A CN201410853546.1A CN201410853546A CN104538309A CN 104538309 A CN104538309 A CN 104538309A CN 201410853546 A CN201410853546 A CN 201410853546A CN 104538309 A CN104538309 A CN 104538309A
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ldmos
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邢军军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种低导通电阻LDMOS的结构，其漂移区采用超浅槽隔离结构，漂移区两侧采用常规浅槽隔离结构。本发明还公开了上述结构的低导通电阻LDMOS的制作方法，其浅槽隔离结构的形成步骤包括：1)用掩膜遮住有源区，光刻刻蚀，在漂移区两侧形成常规STI的沟槽；2)光刻刻蚀，在漂移区形成超浅STI的沟槽；3)在沟槽内淀积二氧化硅，化学机械研磨，形成常规STI和超浅STI。本发明通过在LDMOS结构中引入一层较浅的STI作为LDMOS漂移区场板介质，并优化其刻蚀的深度和角度，使LDMOS的耐压和导通电阻性能得到了大幅提升。

Description

低导通电阻LDMOS 的结构及制作方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及低导通电阻LDMOS的结构及制作方法。
背景技术
在0.18μm BCD工艺中，使用常规STI(浅槽隔离)作为LDMOS(横向扩散金属氧化物半导体)漂移区场板介质，如图1所示。
作为隔离使用的STI，其深度一般约为角度约为80度。仿真和实际的硅结果表明，LDMOS的导电通路上的Idlin(线性区电流)受这层STI的影响很大，但是由于STI的深度和刻蚀角度的限制，LDMOS的耐压和导通电阻无法做到最优化，所以无法实现低导通电阻的LDMOS。
发明内容
本发明要解决的技术问题之一是提供一种低导通电阻LDMOS的结构，它可以提升LDMOS的耐压和导通电阻性能。
为解决上述技术问题，本发明的低导通电阻LDMOS的漂移区采用超浅槽隔离结构，漂移区两侧采用常规浅槽隔离结构。
本发明要解决的技术问题之二是提供上述结构的低导通电阻LDMOS的制作方法，其形成浅槽隔离结构的步骤包括：
1)用掩膜遮住有源区，通过光刻刻蚀，在漂移区两侧形成常规浅槽隔离结构的沟槽；
2)用掩膜定义超浅槽隔离结构的图形，通过光刻刻蚀，在漂移区形成超浅槽隔离结构的的沟槽；所述超浅槽隔离结构的深度浅于所述常规浅槽隔离结构的深度；
3)在所述常规浅槽隔离结构和超浅槽隔离结构的沟槽内淀积二氧化硅，进行化学机械研磨，形成常规浅槽隔离结构和超浅槽隔离结构。
所述超浅槽隔离结构的深度为
所述超浅槽隔离结构的刻蚀角度为70度。
本发明通过在LDMOS结构中引入一层较浅的STI作为LDMOS漂移区场板介质，并优化其刻蚀的深度和角度，使LDMOS的导通电阻性能较常规STI工艺场板结构的LDMOS的导通电阻提升了30％以上。
附图说明
图1是本发明的带STI结构的LDMOS的结构示意图。其中，STI1为常规STI，STI2为超浅STI。
图2～图3是对本发明的LDMOS进行STI2深度仿真得到的仿真结果图。图中STI2的刻蚀角度均为80度。
图4是对本发明的LDMOS进行STI2角度仿真得到的仿真结果图。图中STI2的深度均为 
图5～图7是本发明在LDMOS中制作STI结构的工艺流程示意图。
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现结合附图，详述如下：
本发明的低导通电阻LDMOS的结构如图1所示，其漂移区两侧采用常规深度的STI(即STI 1)，漂移区内采用深度明显浅于常规STI的超浅STI(即STI2)。
在制作本发明的带STI结构的LDMOS前，本发明先对30V LDMOS进行了STI2深度和角度的仿真。
STI2深度仿真结果参见表1和图2、3所示：
表1 STI2深度仿真结果 
当STI2的深度在之间的时候，击穿电压基本不变，其击穿时候的碰撞电离都发生在漏端的下方；但是当STI2的深度进一步降低到的时候，发现击穿点发生在漂移区的表面了，耐压开始下降。
LDMOS的电阻Rsp随着STI2深度的增加基本呈线性的增加，可以认为LDMOS在线性区工作的时候，线性区电流(Idlin，Vg＝5V，Vd＝0.1V)通路要从漏端硅表面绕过STI2下方再到达源端硅表面，所以浅的STI2深度也就相当于减小了器件的pitch(有效器件的尺寸)，从而增加了Idlin，减小了Rsp，参见图3。
STI2角度仿真结果参见表2和图4所示：
表2 STI2角度仿真结果 
随着STI2刻蚀角度的减小，LDMOS的线性区电流基本呈线性地增加，电阻Rsp则基本呈线性地减小。当STI2的刻蚀角度在60～80度之间的时候，击穿电压变化不大。但当STI2的角度减小到45度时，击穿电压明显减小。
利用上述仿真结果，本发明在制作带STI结构的LDMOS时，将STI2的厚度设计为刻蚀角度设计为70度。其中，STI的主要制作工艺过程参见图5～图7所示，主要包括有如下步骤：
步骤1，用掩膜遮住有源区，通过光刻刻蚀，在LDMOS的漂移区两侧形成常规STI 1的沟槽，如图5所示。STI 1沟槽的刻蚀深度为刻蚀角度为80度。
步骤2，用掩膜定义STI2图形，通过光刻刻蚀，在LDMOS的漂移区形成超浅STI2的沟槽，如图6所示。STI2沟槽的刻蚀深度为刻蚀角度为70度。
步骤3，在常规STI 1和超浅STI2的沟槽内淀积二氧化硅，然后进行CMP(化学机械研磨)，形成常规STI 1和超浅STI2，如图7所示。
上述制作工艺与常规0.18μm BCD制程完全匹配。
使用超浅STI结构后LDMOS的实际硅数据如表3所示：
表3 漂移区长度不同的LDMOS的实际硅数据
从表3可以看到，使用超浅STI作为LDMOS漂移区场板介质后，LDMOS的耐压和导通电阻性能得到了大幅提升。

Claims (6)

1.低导通电阻LDMOS的结构，其特征在于，该LDMOS的漂移区采用超浅槽隔离结构，漂移区两侧采用常规浅槽隔离结构。
2.根据权利要求1所述的LDMOS的结构，其特征在于，所述超浅槽隔离结构的深度为
3.根据权利要求1或2所述的LDMOS的结构，其特征在于，所述超浅槽隔离结构的刻蚀角度为70度。
4.权利要求1所述低导通电阻LDMOS的制作方法，其特征在于，该LDMOS的浅槽隔离结构的形成步骤包括：
1)用掩膜遮住有源区，通过光刻刻蚀，在漂移区两侧形成常规浅槽隔离结构的沟槽；
2)用掩膜定义超浅槽隔离结构的图形，通过光刻刻蚀，在漂移区形成超浅槽隔离结构的的沟槽；所述超浅槽隔离结构的深度浅于所述常规浅槽隔离结构的深度；
3)在所述常规浅槽隔离结构和超浅槽隔离结构的沟槽内淀积二氧化硅，进行化学机械研磨，形成常规浅槽隔离结构和超浅槽隔离结构。
5.根据权利要求4所述的方法，其特征在于，所述超浅槽隔离结构的深度为
6.根据权利要求4或5所述的方法，其特征在于，所述超浅槽隔离结构的刻蚀角度为70度。
CN201410853546.1A 2014-12-31 2014-12-31 低导通电阻ldmos 的结构及制作方法 Pending CN104538309A (zh)

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CN103227144A (zh) * 2013-05-07 2013-07-31 上海华力微电子有限公司 提高高压器件浅沟槽隔离性能的方法
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