CN105914179A - Ldmos sti结构及工艺方法 - Google Patents

Ldmos sti结构及工艺方法 Download PDF

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CN105914179A
CN105914179A CN201610470539.2A CN201610470539A CN105914179A CN 105914179 A CN105914179 A CN 105914179A CN 201610470539 A CN201610470539 A CN 201610470539A CN 105914179 A CN105914179 A CN 105914179A
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sti
ldmos
layer
sti structure
oxide layer
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邢军军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

本发明公开了一种LDMOS STI结构，该STI结构作为LDMOS漂移区场板介质，所述的STI结构是复合沟槽，沟槽内由热氧化层包裹HDP氧化层。本发明所述的LDMOS STI结构，即解决了常规STI深度深，导通电阻无法优化的问题，以及底部拐角比较尖而电场集中的问题；又可以很好的解决STI浅的时候，化学淀积氧化层介质可靠性的问题。从而提升了器件的导通能力，并且提高了耐压能力。本发明还公开了所述LDMOS STI结构的工艺方法。

Description

LDMOS STI结构及工艺方法
技术领域
本发明涉及半导体器件制造领域，特别是指一种LDMOS STI结构。本发明还涉及所述LDMOS STI结构的工艺方法。
背景技术
在0.18μm BCD工艺中，使用常规STI(浅槽隔离结构)作为LDMOS漂移区场板介质，常规STI工艺的LDMOS结构如图1所示，图中在P型外延1中具有常规的STI沟槽，该沟槽一侧为漏区，沟槽的一部分位于多晶硅栅极之下。由于其STI的深度和刻蚀角度的限制，LDMOS的耐压和导通电阻无法做到最优化。主要原因是因为作为隔离使用的STI，其深度约其角度约80度，仿真和实际的硅结果表面，其导电通路上的Idlin电流受这层STI的影响很大，所以无法实现低导通电阻的LDMOS。
另一方面，由于STI的填充介质使用的是化学淀积的氧化层HDP(HDP:高密度等离子体氧化层)，而不是热氧化层，即STI沟槽内只有HDP氧化层，如图2所示，所以介质的可靠性没有Locos(局部场氧化)工艺的氧化层好，影响到了LDMOS的耐压和可靠性。
发明内容
本发明所要解决的技术问题在于提供一种LDMOS的STI结构，优化导通电阻，提高耐压能力。
本发明说要解决的另一技术问题在于提供所述LDMOS的STI结构的工艺方法。
为解决上述问题，本发明所述的LDMOS STI结构，该STI结构作为LDMOS漂移区场板介质，所述的STI结构是复合沟槽，沟槽内由热氧化层包裹HDP氧化层。
为解决上述问题，本发明所述的LDMOS STI结构的工艺方法，包含如下的工艺步骤：
步骤1，在P型外延上一次生长一层二氧化硅层及一层氮化硅层；
步骤2，光刻定义并刻蚀形成STI沟槽；
步骤3，在STI沟槽内淀积一层热氧化层；
步骤4，再进行STI沟槽的光刻及刻蚀，形成的STI沟槽深度大于步骤2形成的STI沟槽；
步骤5，对所有STI沟槽进行HDP氧化层淀积，再进行CMP去除外延表面的氮化硅层及二氧化硅。
所述步骤1中，二氧化硅层的厚度为氮化硅的厚度为
所述步骤3中，通过热氧化层法生成的热氧化层的厚度为
本发明所述的LDMOS STI结构，即解决了常规STI深度深，导通电阻无法优化的问题，以及底部拐角比较尖而电场集中的问题；又可以很好的解决STI浅的时候，HDP氧化层介质可靠性的问题。从而提升了器件的导通能力，并且提高了耐压能力。
附图说明
图1是常规LDMOS器件的结构简图，其具有普通的STI结构。
图2是常规LDMOS STI形貌显微图。
图3～7是本发明LDMOS STI结构形成工艺步骤图。
图8是本发明形成的STI结构形貌显微图。
图9是本发明LDMOS STI结构形成工艺流程图。
附图标记说明
1是P型外延，2是氧化硅层，3是氮化硅层，4是HDP氧化层。
具体实施方式
本发明所述的LDMOS STI结构，该STI结构作为LDMOS漂移区场板介质，所述的STI结构是复合沟槽，如图7所示，STI沟槽内由热氧化层2包裹HDP氧化层4。
本发明主要解决了0.18μm BCD制程上，常规STI工艺场板结构的LDMOS导通电阻无法优化的问题。该STI结构，通过引入一层较浅的STI制程，再在这层浅STI内生长一层左右的热氧化层。后续再进行常规淀积HDP氧化层并CMP的工序。
通过这种新型的STI结构，形成的STI沟槽形貌如图8所示，其STI沟槽侧壁底部圆滑，即解决了常规STI深度过深，导通电阻无法优化的问题，以及底部拐角比较尖而电场集中的问题；又可以解决STI浅的时候，HDP氧化层介质可靠性的问题。从而提升了器件的导通能力，并且提高了耐压能力。对0.18μm BCD工艺LDMOS STI结构漂移区进行了优化。
另外，本发明提供所述的LDMOS STI结构的工艺方法，如图3～7所示，包含如下的工艺步骤：
步骤1，在P型外延上一次生长一层厚度为的二氧化硅层，本实施例选用以及一层厚度为的氮化硅层。本实施例选用如图3。
步骤2，光刻定义并刻蚀形成STI沟槽。如图4。
步骤3，如图5所示，在STI沟槽内淀积一层厚度为的热氧化层，本实施例选择
步骤4，如图6所示，再进行STI沟槽的光刻及刻蚀，形成的STI沟槽深度大于步骤2形成的STI沟槽。
步骤5，如图7所示，对所有STI沟槽进行HDP氧化层淀积，再进行CMP去除外延表面的氮化硅层及二氧化硅。
上述方法形成的STI沟槽的显微图如图8所示，沟槽底部边缘与沟槽侧壁的过渡变得平滑，没有明显的台阶感，沟槽内填充的氧化层为热氧化加HDP淀积工艺形成，使器件具有较好的导通能力及耐压能力。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (4)

1.一种LDMOS STI结构，该STI结构作为LDMOS漂移区场板介质，其特征在于：所述的STI结构是复合沟槽，沟槽内由热氧化层包裹HDP氧化层。
2.制造如权利要求1的所述LDMOS STI结构的工艺方法，其特征在于：包含如下的工艺步骤：
步骤1，在P型外延上一次生长一层二氧化硅层及一层氮化硅层；
步骤2，光刻定义并刻蚀形成STI沟槽；
步骤3，在STI沟槽内淀积一层热氧化层；
步骤4，再进行STI沟槽的光刻及刻蚀，形成的STI沟槽深度大于步骤2形成的STI沟槽；
步骤5，对所有STI沟槽进行HDP氧化层淀积，再进行CMP去除外延表面的氮化硅层及二氧化硅。
3.如权利要求2的所述LDMOS STI结构的工艺方法，其特征在于：所述步骤1中，二氧化硅层的厚度为氮化硅的厚度为
4.如权利要求2的所述LDMOS STI结构的工艺方法，其特征在于：所述步骤3中，通过热氧化层法生成的热氧化层的厚度为
CN201610470539.2A 2016-06-24 2016-06-24 Ldmos sti结构及工艺方法 Pending CN105914179A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416089A (zh) * 2019-07-31 2019-11-05 上海华虹宏力半导体制造有限公司 一种ldmos的制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050112822A1 (en) * 2003-11-21 2005-05-26 Andrej Litwin Method in the fabrication of a monolithically integrated high frequency circuit
CN102064129A (zh) * 2009-11-13 2011-05-18 英特赛尔美国股份有限公司 使用宽度可变的掩模开口形成两个或更多个器件结构的半导体工艺
CN102157384A (zh) * 2011-03-10 2011-08-17 上海宏力半导体制造有限公司 晶体管的制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050112822A1 (en) * 2003-11-21 2005-05-26 Andrej Litwin Method in the fabrication of a monolithically integrated high frequency circuit
CN102064129A (zh) * 2009-11-13 2011-05-18 英特赛尔美国股份有限公司 使用宽度可变的掩模开口形成两个或更多个器件结构的半导体工艺
CN102157384A (zh) * 2011-03-10 2011-08-17 上海宏力半导体制造有限公司 晶体管的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416089A (zh) * 2019-07-31 2019-11-05 上海华虹宏力半导体制造有限公司 一种ldmos的制备方法

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Application publication date: 20160831