JP7133254B2 - 配置装置及び配置方法 - Google Patents

配置装置及び配置方法 Download PDF

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Publication number
JP7133254B2
JP7133254B2 JP2021525257A JP2021525257A JP7133254B2 JP 7133254 B2 JP7133254 B2 JP 7133254B2 JP 2021525257 A JP2021525257 A JP 2021525257A JP 2021525257 A JP2021525257 A JP 2021525257A JP 7133254 B2 JP7133254 B2 JP 7133254B2
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Prior art keywords
dies
substrate
wafer
map data
patterns
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JP2021525257A
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Japanese (ja)
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JPWO2022038745A1 (https=
Inventor
耕平 瀬山
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Shinkawa Ltd
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Shinkawa Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0606—Position monitoring, e.g. misposition detection or presence detection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H10P72/53—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Die Bonding (AREA)
  • Forklifts And Lifting Vehicles (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
JP2021525257A 2020-08-20 2020-08-20 配置装置及び配置方法 Active JP7133254B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/031466 WO2022038745A1 (ja) 2020-08-20 2020-08-20 配置装置及び配置方法

Publications (2)

Publication Number Publication Date
JPWO2022038745A1 JPWO2022038745A1 (https=) 2022-02-24
JP7133254B2 true JP7133254B2 (ja) 2022-09-08

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Family Applications (1)

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JP2021525257A Active JP7133254B2 (ja) 2020-08-20 2020-08-20 配置装置及び配置方法

Country Status (6)

Country Link
US (1) US12112962B2 (https=)
JP (1) JP7133254B2 (https=)
KR (1) KR102442373B1 (https=)
CN (1) CN114402424B (https=)
TW (1) TWI782664B (https=)
WO (1) WO2022038745A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120972470B (zh) * 2025-10-22 2026-01-30 北京中科彼岸集成电路科技有限公司 多芯片高密度连接的光刻技术实现方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507844A (ja) 2004-07-21 2008-03-13 インテル・コーポレーション 複数の電子アセンブリの製造方法
WO2012133760A1 (ja) 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
WO2014046052A1 (ja) 2012-09-23 2014-03-27 国立大学法人東北大学 チップ支持基板、チップ支持方法、三次元集積回路、アセンブリ装置及び三次元集積回路の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4720469B2 (ja) 2005-12-08 2011-07-13 株式会社ニコン 貼り合わせ半導体装置製造用の露光方法
US7808613B2 (en) * 2006-08-03 2010-10-05 Asml Netherlands B.V. Individual wafer history storage for overlay corrections
KR100793271B1 (ko) * 2006-12-22 2008-01-10 세크론 주식회사 프로빙 검사장치용 맵 데이터 작성 방법, 및 이를 이용한반도체 칩 검사 방법
EP2539773B1 (en) * 2010-02-26 2014-04-16 Micronic Mydata AB Method and apparatus for performing pattern alignment
CN102263039B (zh) * 2010-05-24 2013-08-14 日月光半导体制造股份有限公司 晶粒总成的制造方法
JP2014060249A (ja) * 2012-09-18 2014-04-03 Hitachi High-Tech Instruments Co Ltd ダイボンダ、および、ダイの位置認識方法
TWI567859B (zh) * 2014-02-10 2017-01-21 新川股份有限公司 安裝裝置及其偏移量修正方法
JP6329665B2 (ja) * 2017-04-03 2018-05-23 ファスフォードテクノロジ株式会社 ダイボンダ及びボンディング方法
TWI744849B (zh) * 2019-04-15 2021-11-01 日商新川股份有限公司 接合裝置以及接合頭的移動量補正方法
JP7575937B2 (ja) * 2020-12-21 2024-10-30 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507844A (ja) 2004-07-21 2008-03-13 インテル・コーポレーション 複数の電子アセンブリの製造方法
WO2012133760A1 (ja) 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
WO2014046052A1 (ja) 2012-09-23 2014-03-27 国立大学法人東北大学 チップ支持基板、チップ支持方法、三次元集積回路、アセンブリ装置及び三次元集積回路の製造方法

Also Published As

Publication number Publication date
CN114402424A (zh) 2022-04-26
CN114402424B (zh) 2025-09-12
WO2022038745A1 (ja) 2022-02-24
US12112962B2 (en) 2024-10-08
KR20220023747A (ko) 2022-03-02
TW202209541A (zh) 2022-03-01
KR102442373B1 (ko) 2022-09-14
TWI782664B (zh) 2022-11-01
JPWO2022038745A1 (https=) 2022-02-24
US20220319885A1 (en) 2022-10-06

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