JP7128225B2 - 電気経路を備えたパッケージ - Google Patents
電気経路を備えたパッケージ Download PDFInfo
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- JP7128225B2 JP7128225B2 JP2020049556A JP2020049556A JP7128225B2 JP 7128225 B2 JP7128225 B2 JP 7128225B2 JP 2020049556 A JP2020049556 A JP 2020049556A JP 2020049556 A JP2020049556 A JP 2020049556A JP 7128225 B2 JP7128225 B2 JP 7128225B2
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
この出願は、2019年3月22日に提出された「PACKAGE WITH ELECTRIC PATHWAY」と題する米国仮出願第62/822,689の利益を主張し、その開示全体が、あらゆる目的のために参照により、本明細書に組み込まれる。
Claims (18)
- 積層基板であって、
第1の端子および第2の端子を有する第1の層であって、前記第1の層が、第1の側部及び前記第1の側部とは異なる第2の側部を含む複数の側部を有する水平主面を有し、前記第1の端子が前記第1の側部に配置され、前記第2の端子が前記第2の側部に配置される、第1の層と、
伝導性要素を有する第2の層と、
前記第1の端子を前記伝導性要素に電気的に接続する第1のビアと、
前記第2の端子を前記伝導性要素に電気的に接続して、前記積層基板内で前記第1の端子と前記第2の端子を電気的に結合する第2のビアと、を含む積層基板と、
前記積層基板に、取り付けられ、電気的に接続されるダイと、を備え、前記ダイが前記積層基板を通して前記第1の端子に電気的に接続され、
前記第1の層が、第3の端子および第4の端子を備え、前記第2の層が、第2の伝導性要素を備え、前記第1および第2の端子が、前記第2の層の前記伝導性要素を通じて電気的に結合され、前記第3および第4の端子が、前記第2の層の前記第2の伝導性要素を通じて電気的に結合され、前記第1および第2の端子からは絶縁されている、集積デバイスパッケージ。 - 前記積層基板が、前記第1の端子に電気的に結合されるパッドを有する最上層をさらに備え、前記パッドが、前記ダイに電気的に接続される、請求項1に記載の集積デバイスパッケージ。
- 前記第2の層の前記伝導性要素が、金属トレースを備えた、請求項1に記載の集積デバイスパッケージ。
- 前記第2の層の前記伝導性要素が、金属板である、請求項1に記載の集積デバイスパッケージ。
- 前記積層基板が、第2の伝導性要素を備えた第3の層をさらに備えた、請求項1に記載の集積デバイスパッケージ。
- 前記第1の層が、第1の伝導性プレートを備えた、請求項1に記載の集積デバイスパッケージ。
- 前記第1の伝導性プレートが、熱伝導性パドルを備えた、請求項6に記載の集積デバイスパッケージ。
- 前記熱伝導性パドルが、前記積層基板の底面に露出し、前記底面が、前記積層基板の最上面に対向し、前記ダイが、前記最上面に取り付けられる、請求項7に記載の集積デバイスパッケージ。
- 前記第1の端子が、ジャンパーを通じて別の集積デバイスパッケージの端子に接続され、それにより、前記他のパッケージの前記端子、前記第1の端子、および前記第2の端子が電気的に結合され、前記ジャンパーが表面トレースを備える、請求項1に記載の集積デバイスパッケージ。
- 前記ダイが、スイッチダイを備える、請求項1に記載の集積デバイスパッケージ。
- 前記スイッチダイが、クワッド単極単投(SPST)ダイを備える、請求項10に記載の集積デバイスパッケージ。
- 前記ダイが第1のダイであって、前記集積デバイスパッケージが、前記第1のダイ上に配置された第2のダイおよび前記第1のダイと前記第2のダイの間に配置された第3のダイをさらに備え、前記第2のダイが、前記第1のダイを制御するように構成されたコントローラを備え、前記コントローラが、シリアルパラレルインターフェース(SPI)コンバータを備え、前記第3のダイが、第2のクワッドSPSTダイを備え、前記第2のダイが、前記第3のダイを制御するように構成されている、請求項11に記載の集積デバイスパッケージ。
- 第1の端子および第2の端子を有する第1の層であって、前記第1の層が、第1の側部及び前記第1の側部とは異なる第2の側部を含む複数の側部を有する水平主面を有し、前記第1の端子が前記第1の側部に配置され、前記第2の端子が前記第2の側部に配置される、第1の層と、
伝導性要素を有する第2の層と、
集積デバイスダイに接続するように構成されたパッドを有する第3の層と、
前記第1の端子を前記伝導性要素に電気的に接続する第1のビアと、
前記第2の端子を前記伝導性要素に電気的に接続する第2のビアと、を備え、
前記第1の層が、第3の端子および第4の端子を備え、前記第2の層が、第2の伝導性要素を備え、前記第1および第2の端子が、前記第2の層の前記伝導性要素を通じて電気的に結合され、前記第3および第4の端子が、前記第2の層の前記第2の伝導性要素を通じて電気的に結合され、前記第1および第2の端子からは絶縁されている、積層基板。 - 前記第2の層の前記伝導性要素が、金属トレースを備える、請求項13に記載の積層基板。
- 前記第3の層が第2の伝導性要素を有する、請求項13に記載の積層基板。
- 最上面および前記最上面の反対側の底面を有する積層基板であって、
前記底面上の第1の端子および第2の端子であって、前記底面が、第1の側部及び前記第1の側部とは異なる第2の側部を含む複数の側部を有し、前記第1の端子が前記第1の側部に配置され、前記第2の端子が前記第2の側部に配置される、第1の端子および第2の端子と、
前記最上面上のパッドと、
前記第1の端子と前記第2の端子を電気的に結合するための電気経路と、を含む積層基板と、
前記積層基板の最上面上の前記パッドに電気的に接続されるダイと、を備え、前記ダイが前記積層基板を通して前記第1の端子に電気的に接続され、
前記底面が、第3の端子および第4の端子を備え、前記第1および第2の端子が、前記電気経路を通じて電気的に結合され、前記第3および第4の端子が、前記電気経路と同じ層に配置された別の電気経路を通じて電気的に結合され、前記第1および第2の端子からは絶縁されている、集積デバイスパッケージ。 - 前記電気経路が、第1のビアと、前記第1のビアおよび前記第1の端子に電気的に結合された伝導性要素とを含み、それにより、前記伝導性要素と前記第1の端子が、第1のビアを経由して電気的に接続される、請求項16に記載の集積デバイスパッケージ。
- 前記電気経路が、前記伝導性要素と前記第2の端子とを電気的に接続する第2のビアをさらに備える、請求項17に記載の集積デバイスパッケージ。
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US201962822689P | 2019-03-22 | 2019-03-22 | |
US62/822,689 | 2019-03-22 | ||
US16/749,855 US11222834B2 (en) | 2019-03-22 | 2020-01-22 | Package with electrical pathway |
US16/749,855 | 2020-01-22 |
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JP2020155777A JP2020155777A (ja) | 2020-09-24 |
JP7128225B2 true JP7128225B2 (ja) | 2022-08-30 |
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