JP7092456B2 - 連続ｃｖｄプロセスによる低フッ素タングステンの堆積 - Google Patents

連続ｃｖｄプロセスによる低フッ素タングステンの堆積 Download PDF

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JP7092456B2
JP7092456B2 JP2016104837A JP2016104837A JP7092456B2 JP 7092456 B2 JP7092456 B2 JP 7092456B2 JP 2016104837 A JP2016104837 A JP 2016104837A JP 2016104837 A JP2016104837 A JP 2016104837A JP 7092456 B2 JP7092456 B2 JP 7092456B2
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tungsten
substrate
containing precursor
layer
bulk
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JP2017008412A (ja
JP2017008412A5 (enrdf_load_stackoverflow
Inventor
アダム・ジャンドル
サンジャイ・ゴピナス
シャオラン・バ
ラシーナ・フマユン
ミハル・ダネク
ローレンス・シュロス
ティアンファ・ユ
シュルティ・ビベク・トンバレ
カイハン・アビディ・アシュティアニ
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Lam Research Corp
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Lam Research Corp
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Priority claimed from US14/723,270 external-priority patent/US9613818B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14—Deposition of only one other metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2016104837A 2015-05-27 2016-05-26 連続ｃｖｄプロセスによる低フッ素タングステンの堆積 Active JP7092456B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US14/723,270 2015-05-27
US14/723,270 US9613818B2 (en) 2015-05-27 2015-05-27 Deposition of low fluorine tungsten by sequential CVD process
US201662328759P 2016-04-28 2016-04-28
US62/328,759 2016-04-28

Publications (3)

Publication Number Publication Date
JP2017008412A JP2017008412A (ja) 2017-01-12
JP2017008412A5 JP2017008412A5 (enrdf_load_stackoverflow) 2021-08-26
JP7092456B2 true JP7092456B2 (ja) 2022-06-28

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JP2016104837A Active JP7092456B2 (ja) 2015-05-27 2016-05-26 連続ｃｖｄプロセスによる低フッ素タングステンの堆積

Country Status (3)

Country Link
JP (1) JP7092456B2 (enrdf_load_stackoverflow)
KR (1) KR102397797B1 (enrdf_load_stackoverflow)
TW (1) TWI747825B (enrdf_load_stackoverflow)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI672737B (zh) * 2013-12-27 2019-09-21 美商蘭姆研究公司 允許低電阻率鎢特徵物填充之鎢成核程序
JP6788545B2 (ja) * 2017-04-26 2020-11-25 東京エレクトロン株式会社 タングステン膜を形成する方法
JP6946463B2 (ja) * 2017-06-05 2021-10-06 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ ワードライン抵抗を低下させる方法
JP2020526669A (ja) * 2017-07-13 2020-08-31 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ タングステン核形成層を堆積させるための方法及び装置
KR102424993B1 (ko) 2017-09-11 2022-07-25 에스케이하이닉스 주식회사 반도체 장치의 제조방법
US10669160B2 (en) * 2018-04-30 2020-06-02 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Heterogeneous wet synthesis process for preparation of high purity tungsten pentahalide
KR102513403B1 (ko) * 2018-07-30 2023-03-24 주식회사 원익아이피에스 텅스텐 증착 방법
CN112533873A (zh) * 2018-08-17 2021-03-19 中央硝子株式会社 六氟化钨的制造方法
JP7138518B2 (ja) 2018-08-31 2022-09-16 東京エレクトロン株式会社 成膜方法及び成膜システム
CN111162039A (zh) * 2018-11-08 2020-05-15 长鑫存储技术有限公司 金属导电结构及半导体器件的制备方法
WO2020123987A1 (en) * 2018-12-14 2020-06-18 Lam Research Corporation Atomic layer deposition on 3d nand structures
KR20200099112A (ko) 2019-02-13 2020-08-21 세종대학교산학협력단 Ald 공정에서 금속 전구체 환원용 환원제 조성물 및 금속 박막의 형성 방법
TWI831915B (zh) * 2019-02-20 2024-02-11 日商東京威力科創股份有限公司 半導體裝置之製造方法
KR20210141762A (ko) 2019-04-11 2021-11-23 램 리써치 코포레이션 고 단차 커버리지 (step coverage) 텅스텐 증착
US11447864B2 (en) * 2019-04-19 2022-09-20 Asm Ip Holding B.V. Layer forming method and apparatus
KR20210158419A (ko) 2019-05-22 2021-12-30 램 리써치 코포레이션 핵생성-프리 텅스텐 증착
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition
JP2021038442A (ja) * 2019-09-04 2021-03-11 東京エレクトロン株式会社 基板処理方法及び基板処理装置
TW202206634A (zh) * 2020-06-30 2022-02-16 美商應用材料股份有限公司 在低溫下的選擇性鎢沉積
KR102847592B1 (ko) 2020-11-05 2025-08-18 세종대학교산학협력단 텅스텐 전구체, 이를 이용한 텅스텐 박막 증착 방법 및 증착 장치
WO2022108908A1 (en) * 2020-11-20 2022-05-27 Lam Research Corporation Low resistance pulsed cvd tungsten
US11515200B2 (en) * 2020-12-03 2022-11-29 Applied Materials, Inc. Selective tungsten deposition within trench structures
JP7733133B2 (ja) * 2021-05-07 2025-09-02 インテグリス・インコーポレーテッド モリブデンまたはタングステン材料の堆積方法
CN114420533B (zh) * 2021-12-08 2024-10-18 武汉新芯集成电路股份有限公司 在半导体晶片上制备钨的方法
CN119230478A (zh) * 2023-06-30 2024-12-31 北京北方华创微电子装备有限公司 沉积钨塞的工艺方法及半导体器件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008303466A (ja) 2001-10-10 2008-12-18 Applied Materials Inc 一連の堆積技術を用いる耐火性金属層を堆積する方法
JP2009024252A (ja) 2007-05-15 2009-02-05 Applied Materials Inc タングステン材料の原子層堆積法
JP2015067869A (ja) 2013-09-30 2015-04-13 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6936538B2 (en) * 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US8551885B2 (en) * 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
KR101356332B1 (ko) * 2010-03-19 2014-02-04 노벨러스 시스템즈, 인코포레이티드 낮은 저항 및 강한 미소-접착 특성을 가진 텅스텐 박막의 증착 방법
US8975142B2 (en) * 2013-04-25 2015-03-10 Globalfoundries Inc. FinFET channel stress using tungsten contacts in raised epitaxial source and drain

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008303466A (ja) 2001-10-10 2008-12-18 Applied Materials Inc 一連の堆積技術を用いる耐火性金属層を堆積する方法
JP2009024252A (ja) 2007-05-15 2009-02-05 Applied Materials Inc タングステン材料の原子層堆積法
JP2015067869A (ja) 2013-09-30 2015-04-13 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム

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JP2017008412A (ja) 2017-01-12
TW201715067A (zh) 2017-05-01
TWI747825B (zh) 2021-12-01
KR20160140448A (ko) 2016-12-07
KR102397797B1 (ko) 2022-05-12

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