JP7054344B2 - 基板に多層構造を作るための方法及び多層デバイス - Google Patents
基板に多層構造を作るための方法及び多層デバイス Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 63
- 238000000034 method Methods 0.000 title claims description 48
- 238000005530 etching Methods 0.000 claims description 66
- 238000001020 plasma etching Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 50
- 239000000463 material Substances 0.000 description 15
- 230000008569 process Effects 0.000 description 15
- 238000010884 ion-beam technique Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 4
- 238000003631 wet chemical etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Description
Claims (12)
- 基板に多層構造を作るための方法であって、
該方法は、
前記基板の上に配置されるデバイス積層の上にマスクを供給するステップであって、前記デバイス積層は、第1の層のタイプ及び第2の層のタイプから成る、第1の複数の層を備える、ステップと、
前記基板の平面の法線に対して第1のゼロ以外の入射角を形成して、第1のイオンを第1の方向に沿って向けるステップであって、前記法線に対して第1のゼロ以外の傾射角を形成する側壁の角度を有する第1の側壁が形成され、前記第1の側壁は、前記第1の複数の層の少なくとも一部からの、及び、前記第1の層のタイプ及び前記第2の層のタイプから成る、第2の複数の層を備える、ステップと、
前記第2の複数の層を、第1の選択エッチングを用いてエッチングし、前記第1の層のタイプを、前記第2の層のタイプに対して、選択的にエッチングするステップであって、階段構造を有し、前記法線に対してゼロ以外の傾斜角を有する第1の平均側壁角度を規定する第1の側壁構造が形成され、該第1の側壁構造の階段表面は前記第1の平均側壁角度に対して傾斜している、ステップと、を有し、
前記第1のイオンは不活性ガスイオンを含み、
前記第2の複数の層は、少なくとも16の層の対を備え、少なくとも1つの層の対はシリコン層及び絶縁材料層を含む方法。 - 前記第2の複数の層を、第2の選択エッチングを用いてエッチングし、前記第2の層のタイプを、前記第1の層のタイプに対して、選択的にエッチングするステップをさらに有する、請求項1記載の基板に多層構造を作るための方法。
- 前記第2の複数の層を、前記第1の選択エッチングを用いてエッチングする前記ステップは、第1の反応性イオンエッチングを実施して、前記第1の層のタイプをエッチングするステップを有し、前記第2の複数の層を、前記第2の選択エッチングを用いてエッチングする前記ステップは、前記第1の反応性イオンエッチングと異なる第2の反応性イオンエッチングを実施して、前記第2の層のタイプをエッチングするステップを有する、請求項2記載の基板に多層構造を作るための方法。
- 前記法線に対して第2のゼロ以外の入射角を形成して、第2のイオンを前記第1の方向とは異なる第2の方向に沿って向けるステップであって、前記法線に対してゼロ以外の傾斜角を有する第2の平均側壁角度を規定する第2の側壁が形成され、前記第2の側壁は、前記第1の複数の層の少なくとも一部からの、及び、前記第1の層のタイプ及び前記第2の層のタイプから成る、第3の複数の層を備える、ステップと、
前記第3の複数の層を、第3の選択エッチングを用いてエッチングし、前記第1の層のタイプを、前記第2の層のタイプに対して、選択的にエッチングするステップであって、階段構造を有し、前記法線に対してゼロ以外の傾斜角を有する第2の平均側壁角度を規定する第2の側壁構造が形成され、該第2の側壁構造の階段表面は前記第2の平均側壁角度に対して傾斜している、ステップと、をさらに有する、請求項1記載の基板に多層構造を作るための方法。 - 前記第1のイオンは、50KeVより小さいエネルギーを有するイオンを含む、請求項1記載の基板に多層構造を作るための方法。
- 前記デバイス積層は、シリコン層及び絶縁材料層を含む交互になっている層を備える、請求項1記載の基板に多層構造を作るための方法。
- 前記第1の方向は、前記法線に対して15度と70度との間の入射角を形成する、請求項1記載の基板に多層構造を作るための方法。
- 前記第1の層のタイプは、前記第2の層のタイプと交互になる仕方で配置される、請求項1記載の基板に多層構造を作るための方法。
- 基板に多層構造を作るための方法であって、
該方法は、
前記基板の上に配置されるデバイス積層の上にマスクを供給するステップであって、前記デバイス積層は、第1の層のタイプ及び第2の層のタイプから成る、第1の複数の層を備える、ステップと、
前記基板の平面の法線に対して第1のゼロ以外の入射角を形成して、第1のイオンを第1の方向に沿って向けるステップであって、前記法線に対して第1のゼロ以外の傾射角を形成する側壁の角度を有する第1の側壁が形成され、前記第1の側壁は、前記第1の複数の層の少なくとも一部からの、及び、前記第1の層のタイプ及び前記第2の層のタイプから成る、第2の複数の層を備える、ステップと、
前記第2の複数の層を、第1の選択エッチングを用いてエッチングし、前記第1の層のタイプを、前記第2の層のタイプに対して、選択的にエッチングするステップであって、階段構造を有し、前記法線に対してゼロ以外の傾斜角を有する第1の平均側壁角度を規定する第1の側壁構造が形成され、前記第1の層のタイプ又は前記第2の層のタイプの少なくとも1つの層は、前記第1の平均側壁角度に対して傾斜している階段表面を備え、電気コンタクトは前記階段表面上に形成される、ステップと、
を有し、
前記第1のイオンは不活性ガスイオンを含み、
前記第2の複数の層は、少なくとも16の層の対を備え、少なくとも1つの層の対はシリコン層及び絶縁材料層を含み、
前記デバイス積層はVNANDデバイスを備える、方法。 - 前記第2の複数の層を、第2の選択エッチングを用いてエッチングし、前記第2の層のタイプを、前記第1の層のタイプに対して、選択的にエッチングするステップをさらに有する、請求項9記載の基板に多層構造を作るための方法。
- 前記法線に対して第2のゼロ以外の入射角を形成して、第2のイオンを前記第1の方向とは異なる第2の方向に沿って向けるステップであって、前記法線に対してゼロ以外の傾斜角を有する第2の平均側壁角度を規定する第2の側壁が形成され、前記第2の側壁は、前記第1の複数の層の少なくとも一部からの、及び、前記第1の層のタイプ及び前記第2の層のタイプから成る、第3の複数の層を備える、ステップと、
前記第2の側壁に沿って前記第1の層のタイプの少なくとも1つの層への第2の電気コンタクトを形成するステップと、をさらに有する、請求項9記載の基板に多層構造を作るための方法。 - 基板の上に配置される不均質デバイス積層であって、該不均質デバイス積層は、多層であり、第1の層のタイプの少なくとも1つの層及び第2の層のタイプの少なくとも1つの層を備える不均質デバイス積層と、
基板の平面の法線に対してゼロ以外の傾斜角を有する第1の平均側壁角度を規定する少なくとも1つの側壁と、
前記第1の平均側壁角度と異なる第2の平均側壁角度を規定する追加の少なくとも1つの側壁と、を備え、
前記第2の平均側壁角度は、前記基板の平面の前記法線に対して第2のゼロ以外の傾斜角を有し、
前記少なくとも1つの側壁及び前記追加の少なくとも1つの側壁は、同じ数の階段表面を含む階段構造を備え、
前記多層の複数の層は、少なくとも16の層の対を備え、少なくとも1つの層の対はシリコン層及び絶縁材料層を含み、
前記不均質デバイス積層はVNANDデバイスを備える、多層デバイス。
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