JP7040976B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7040976B2 JP7040976B2 JP2018064309A JP2018064309A JP7040976B2 JP 7040976 B2 JP7040976 B2 JP 7040976B2 JP 2018064309 A JP2018064309 A JP 2018064309A JP 2018064309 A JP2018064309 A JP 2018064309A JP 7040976 B2 JP7040976 B2 JP 7040976B2
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- 239000004065 semiconductor Substances 0.000 title claims description 140
- 230000005684 electric field Effects 0.000 claims description 88
- 238000009792 diffusion process Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000002040 relaxant effect Effects 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 55
- 230000000052 comparative effect Effects 0.000 description 9
- 230000007547 defect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 239000002344 surface layer Substances 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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Description
図1および図2を参照して、本実施の形態に係る半導体装置10について説明する。図1に示すように、半導体装置10は半導体の基板12、基板12の一方の主面50内に形成されたP拡散層14(P型の不純物が拡散された領域)、N-拡散層16(N型の不純物が比較的低濃度で拡散された領域)、N型の不純物が拡散されたソース領域18、N型の不純物が拡散されたドレイン領域20、ドリフト層38、およびSTI部34を含んで構成されている。P型拡散層14とN-拡散層16との界面によりPN接合PNが形成されている。
なお、拡張ゲート電極42の角部S1、S2、S3の位置は、電界集中点E1、E2と重ならない位置に電界集中点が発生するように決めることが望ましい。
図3を参照して、本実施の形態に係る半導体装置10Aについて説明する。半導体装置10Aは、上記実施の形態に係る半導体装置10において拡張ゲート電極42に相当する部分の構成を変えた形態である。従って、半導体装置10と同様の構成には同じ符号を付して詳細な説明を省略する。
図4を参照して、本実施の形態に係る半導体装置10Bについて説明する。半導体装置10Bは、上記実施の形態に係る半導体装置10において拡張ゲート電極42に相当する部分の構成を変えた形態である。従って、半導体装置10と同様の構成には同じ符号を付して詳細な説明を省略する。
図5から図7を参照して、本実施の形態に係る半導体装置10Cについて説明する。半導体装置10Cは、半導体装置70(図9参照)においてゲート酸化膜26の形状を変えた形態である。従って、半導体装置10と同様の構成には同じ符号を付して詳細な説明を省略する。
図8を参照して、本実施の形態にかかる半導体装置10Dについて説明する。半導体装置10Dは、上記実施の形態に係る半導体装置10Cにおけるドリフト層38をドリフト層38Aに変えた形態である。従って、半導体装置10Cと同様の構成には同じ符号を付して詳細な説明を省略する。図8(a)は半導体装置10Dの構成の一例を示し、図8(b)は本実施の形態に係る半導体装置10Dにおける電界分布をシミュレーションした結果、図8(c)は比較のために半導体装置10Cにおける電界分布をシミュレーションした結果を示している。
12 基板
14 P拡散層
16 N-拡散層
18 ソース領域
20 ドレイン領域
22 ソース端子
24 ドレイン端子
26 ゲート酸化膜
28 ゲート電極
30、30-1、30-2 ゲート端子
32-1、32-2 サイドウォール
34 STI部
36 厚膜部
38、38A ドリフト層
40 P型注入領域
42 拡張ゲート電極
44 第2ゲート電極
50 主面
70 半導体装置
72 基板
74 P層
76 N-層
78 ソース領域
80 ドレイン領域
82 ソース端子
84 ドレイン端子
86 ゲート酸化膜
88 ゲート電極
90 ゲート端子
94 STI部
98 ドリフト層
E1、E2 電界集中点
PN PN接合
S1~S3 角部
T 端部
Claims (12)
- 半導体基板と、
前記半導体基板の一主面内に形成された第1導電型のソース領域と、
前記一主面内に形成されるとともにチャネル領域を介して前記ソース領域と接続された第1導電型のドレイン領域と、
前記チャネル領域上に絶縁膜を介して形成されたゲート電極と、
前記ゲート電極の下部から前記ドレイン領域までの間の前記一主面内に形成された第1導電型のドリフト層と、
前記ゲート電極の下部に一端を有し、前記ドレイン領域と接する位置に他端を有する開口を備えるとともに前記一主面から前記半導体基板に予め定められた深さで前記ドリフト層を縦断して形成された溝部と、
前記一端の近傍に設けられるとともに前記ソース領域とドレイン領域との間に発生する電界を緩和させる電界緩和部と、
前記ソース領域を含むように前記一主面内に形成された第2導電型の第1の領域と、
前記ドレイン領域を含むように前記一主面内に形成されるとともに不純物濃度が前記ドリフト層より低くされた第1導電型の第2の領域と、
を含み、
前記第1の領域と前記第2の領域との界面が前記ゲート電極の下部に位置する
半導体装置。 - 前記ドリフト層は、前記一主面からの距離を異ならせて形成された第1導電型の複数の拡散層を含む
請求項1に記載の半導体装置。 - 前記溝部の内部が絶縁物で埋め込まれている
請求項1又は請求項2に記載の半導体装置。 - 前記電界緩和部は、前記溝部の内部に設けられた電界緩和電極である
請求項1から請求項3のいずれか1項に記載の半導体装置。 - 前記電界緩和電極は、前記ゲート電極から前記絶縁膜を縦断して前記溝部の内部まで延伸して形成された拡張ゲート電極である
請求項4に記載の半導体装置。 - 前記電界緩和電極は、前記ゲート電極とは別に前記溝部の内部に形成された第2のゲート電極である
請求項4に記載の半導体装置。 - 前記電界緩和部は、前記一端に接続される前記溝部の側面に対向して設けられた1または複数の角部を備える
請求項1から請求項6のいずれか1項に記載の半導体装置。 - 前記電界緩和部はポリシリコンで形成されている
請求項1から請求項7のいずれか1項に記載の半導体装置。 - 前記ゲート電極および前記絶縁膜の両側に形成されたサイドウォールをさらに含み、
前記一端が前記ドレイン領域側の前記サイドウォールの下部に配置された
請求項1から請求項3のいずれか1項に記載の半導体装置。 - 前記電界緩和部は、前記一端の上部において前記絶縁膜が厚く形成された厚膜部である 請求項1から請求項3のいずれか1項に記載の半導体装置。
- 前記電界緩和部は、前記一端の近傍において前記ドリフト層に注入された第2導電型の注入領域である
請求項1から請求項3、および請求項10のいずれか1項に記載の半導体装置。 - 前記ドリフト層は、前記一主面からの距離を異ならせて形成された第1導電型の複数の拡散層を含み
前記注入領域は前記複数の拡散層の最も前記一主面に近い拡散層に注入されている
請求項11に記載の半導体装置。
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US16/355,620 US20190305129A1 (en) | 2018-03-29 | 2019-03-15 | Semiconductor device |
CN201910212232.6A CN110323279B (zh) | 2018-03-29 | 2019-03-20 | 半导体装置 |
US17/097,115 US11929432B2 (en) | 2018-03-29 | 2020-11-13 | Semiconductor device |
JP2022036355A JP7315743B2 (ja) | 2018-03-29 | 2022-03-09 | 半導体装置 |
JP2023115530A JP2023126448A (ja) | 2018-03-29 | 2023-07-13 | 半導体装置 |
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US11387353B2 (en) * | 2020-06-22 | 2022-07-12 | Globalfoundries U.S. Inc. | Structure providing charge controlled electronic fuse |
US11705515B2 (en) * | 2021-03-05 | 2023-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate electrode extending into a shallow trench isolation structure in high voltage devices |
US20220293729A1 (en) * | 2021-03-11 | 2022-09-15 | Taiwan Semiconductor Manufacturing Company Limited | Field effect transistor including a downward-protruding gate electrode and methods for forming the same |
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US20210066496A1 (en) | 2021-03-04 |
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