JP7021369B2 - 湿気保護封止を有するパッケージ化された電子回路とその形成方法 - Google Patents
湿気保護封止を有するパッケージ化された電子回路とその形成方法 Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (10)
- 電子回路を製作する方法であって、
第1の温度で、第1の金属層の一部分上に第1のポリマー層を形成するステップと、
前記第1の金属層と反対側の前記第1のポリマー層上に第2の金属層を形成するステップと、
第2の温度で、前記第2の金属層上及び前記第1のポリマー層上に誘電体層を形成するステップであって、前記第2の温度は前記第1の温度未満である、ステップと、
第3の温度で、前記誘電体層上に第2のポリマー層を形成するステップであって、前記第3の温度は前記第2の温度未満である、ステップと
を含み、
前記誘電体層は第2の誘電体層を備え、前記方法は、前記第2の金属層を形成する前に、前記第1の金属層上に第1の誘電体層を形成するステップをさらに含み、前記第1の金属層、前記第1の誘電体層、及び前記第2の金属層は、キャパシタを形成する、方法。 - 前記第1の金属層は基板上に形成され、前記第1のポリマー層は、前記第1の金属層と、前記第2の金属層の周辺部との間に形成され、前記第1のポリマー層は、前記基板の上部表面に垂直な方向に、前記第1の誘電体層の厚さより大きな厚さを有する、請求項1に記載の方法。
- 前記第2の金属層の前記周辺部は、前記第2の金属層の中心より、前記第1の金属層の上に離れて間隔が空けられる、請求項2に記載の方法。
- 前記第1のポリマー層は、前記第2の金属層の第1の端部と前記第1の金属層との間にある、請求項2に記載の方法。
- 前記第2の誘電体層は、シリコンと、酸素又は窒素の少なくとも1つとを含み、前記第1及び第2のポリマー層はそれぞれ炭素ベースの層である、請求項1から4までのいずれか一項に記載の方法。
- 前記第2の誘電体層及び前記第2のポリマー層は、ウェハ上に形成され、前記方法は、前記第2の誘電体層及び前記第2のポリマー層の形成後に、前記ウェハを個々のチップにダイシングするステップをさらに含む、請求項1から5までのいずれか一項に記載の方法。
- 前記第2の金属層は、トランジスタのゲート電極とゲート・フィンガとの間に結合されたゲート・ジャンパを備える、請求項1に記載の方法。
- 前記第1の金属層は、実質的に同じ瞬時電流方向を有する自己結合区間を含んだ金属トレースを備える、請求項1から7までのいずれか一項に記載の方法。
- 前記第1の金属層は、基板上に形成され、前記方法は、前記基板上に複数のトランジスタを形成するステップをさらに含み、前記誘電体層は、前記トランジスタの上部表面上に形成され、前記第2のポリマー層は、前記トランジスタの前記上部表面上に形成されない、請求項1から8までのいずれか一項に記載の方法。
- 前記第1の温度は200~450℃の間であり、前記第2の温度は180~400℃の間であり、前記第3の温度は150~240℃の間である、請求項1に記載の方法。
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JP2022015567A JP7375060B2 (ja) | 2018-04-24 | 2022-02-03 | 湿気保護封止を有するパッケージ化された電子回路とその形成方法 |
JP2023183339A JP2024010101A (ja) | 2018-04-24 | 2023-10-25 | 湿気保護封止を有するパッケージ化された電子回路とその形成方法 |
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US15/960,693 | 2018-04-24 | ||
US15/960,693 US10811370B2 (en) | 2018-04-24 | 2018-04-24 | Packaged electronic circuits having moisture protection encapsulation and methods of forming same |
PCT/US2019/026885 WO2019209543A1 (en) | 2018-04-24 | 2019-04-11 | Packaged electronic circuits having moisture protection encapsulation and methods of forming same |
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JP2022015567A Active JP7375060B2 (ja) | 2018-04-24 | 2022-02-03 | 湿気保護封止を有するパッケージ化された電子回路とその形成方法 |
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US (2) | US10811370B2 (ja) |
EP (1) | EP3785295A1 (ja) |
JP (3) | JP7021369B2 (ja) |
KR (3) | KR102607843B1 (ja) |
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US20210175138A1 (en) * | 2019-12-05 | 2021-06-10 | Cree, Inc. | Semiconductors Having Die Pads with Environmental Protection and Process of Making Semiconductors Having Die Pads with Environmental Protection |
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- 2019-04-11 JP JP2020556898A patent/JP7021369B2/ja active Active
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JP7375060B2 (ja) | 2023-11-07 |
US10811370B2 (en) | 2020-10-20 |
EP3785295A1 (en) | 2021-03-03 |
JP2024010101A (ja) | 2024-01-23 |
KR20230164246A (ko) | 2023-12-01 |
KR20220126799A (ko) | 2022-09-16 |
JP2022058877A (ja) | 2022-04-12 |
KR102607843B1 (ko) | 2023-11-30 |
WO2019209543A1 (en) | 2019-10-31 |
US11682634B2 (en) | 2023-06-20 |
KR102440804B1 (ko) | 2022-09-07 |
JP2021521649A (ja) | 2021-08-26 |
US20190326230A1 (en) | 2019-10-24 |
KR20200142030A (ko) | 2020-12-21 |
CN112106188A (zh) | 2020-12-18 |
US20210028127A1 (en) | 2021-01-28 |
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