JP7015691B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7015691B2
JP7015691B2 JP2017252357A JP2017252357A JP7015691B2 JP 7015691 B2 JP7015691 B2 JP 7015691B2 JP 2017252357 A JP2017252357 A JP 2017252357A JP 2017252357 A JP2017252357 A JP 2017252357A JP 7015691 B2 JP7015691 B2 JP 7015691B2
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JP
Japan
Prior art keywords
wiring
semiconductor device
wiring board
mounting portions
mounting
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017252357A
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English (en)
Japanese (ja)
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JP2019117909A5 (https=
JP2019117909A (ja
Inventor
泰愛 堀川
義博 井原
義弘 北
輝 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2017252357A priority Critical patent/JP7015691B2/ja
Priority to US16/214,284 priority patent/US11309224B2/en
Publication of JP2019117909A publication Critical patent/JP2019117909A/ja
Publication of JP2019117909A5 publication Critical patent/JP2019117909A5/ja
Application granted granted Critical
Publication of JP7015691B2 publication Critical patent/JP7015691B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/055—Folded back on itself
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/226—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for HF amplifiers
    • H10W44/234—Arrangements for impedance matching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2017252357A 2017-12-27 2017-12-27 半導体装置 Active JP7015691B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017252357A JP7015691B2 (ja) 2017-12-27 2017-12-27 半導体装置
US16/214,284 US11309224B2 (en) 2017-12-27 2018-12-10 Folded substrate for stacked integrated circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017252357A JP7015691B2 (ja) 2017-12-27 2017-12-27 半導体装置

Publications (3)

Publication Number Publication Date
JP2019117909A JP2019117909A (ja) 2019-07-18
JP2019117909A5 JP2019117909A5 (https=) 2020-09-17
JP7015691B2 true JP7015691B2 (ja) 2022-02-03

Family

ID=66951441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017252357A Active JP7015691B2 (ja) 2017-12-27 2017-12-27 半導体装置

Country Status (2)

Country Link
US (1) US11309224B2 (https=)
JP (1) JP7015691B2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11201096B2 (en) * 2019-07-09 2021-12-14 Texas Instruments Incorporated Packaged device with die wrapped by a substrate
JP7539820B2 (ja) * 2020-11-16 2024-08-26 新光電気工業株式会社 配線基板及び半導体装置
US11710722B2 (en) * 2021-04-16 2023-07-25 Micron Technology, Inc. Semiconductor assemblies with systems and methods for managing high die stack structures
CN113851451B (zh) * 2021-11-30 2022-08-02 江苏长晶科技有限公司 一种基于可塑性基板的芯片3d堆叠的封装结构及其制造方法
KR102899839B1 (ko) * 2021-12-06 2025-12-12 삼성전자주식회사 반도체 패키지 및 그의 검사 방법
CN116660999B (zh) * 2022-02-21 2026-02-17 北京字跳网络技术有限公司 佩戴检测方法、装置、设备、存储介质及计算机程序产品

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002171071A (ja) 2000-12-04 2002-06-14 Ibiden Co Ltd 多層配線基板、及びその製造方法
JP2004228344A (ja) 2003-01-23 2004-08-12 Oki Electric Cable Co Ltd 多層ｆｐｃ
US20040238931A1 (en) 2003-05-30 2004-12-02 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
WO2008055708A2 (de) 2006-11-09 2008-05-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mikroelektronische baugruppe und verfahren zum herstellen einer mikroelektronischen baugruppe
US20080148559A1 (en) 2004-10-13 2008-06-26 Nickerson Robert M Folded substrate with interposer package for integrated circuit devices
US20120261818A1 (en) 2010-05-13 2012-10-18 Stats Chippac, Ltd. Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
WO2013004083A1 (zh) 2011-07-01 2013-01-10 中国科学院微电子研究所 一种基于柔性基板封装的屏蔽结构及其制作工艺

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Publication number Priority date Publication date Assignee Title
US5128831A (en) * 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
JP3110922B2 (ja) * 1993-08-12 2000-11-20 富士通株式会社 マルチチップ・モジュール
US5646446A (en) * 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US6444921B1 (en) * 2000-02-03 2002-09-03 Fujitsu Limited Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
WO2006082620A1 (ja) 2005-01-31 2006-08-10 Spansion Llc 積層型半導体装置及び積層型半導体装置の製造方法
TWI365524B (en) * 2007-10-04 2012-06-01 Unimicron Technology Corp Stackable semiconductor device and fabrication method thereof
US8278141B2 (en) * 2008-06-11 2012-10-02 Stats Chippac Ltd. Integrated circuit package system with internal stacking module
US10192810B2 (en) * 2013-06-28 2019-01-29 Intel Corporation Underfill material flow control for reduced die-to-die spacing in semiconductor packages
CN104637927B (zh) * 2013-11-12 2019-01-22 中国科学院微电子研究所 一种基于柔性基板的三维封装结构及工艺方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002171071A (ja) 2000-12-04 2002-06-14 Ibiden Co Ltd 多層配線基板、及びその製造方法
JP2004228344A (ja) 2003-01-23 2004-08-12 Oki Electric Cable Co Ltd 多層ｆｐｃ
US20040238931A1 (en) 2003-05-30 2004-12-02 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US20080148559A1 (en) 2004-10-13 2008-06-26 Nickerson Robert M Folded substrate with interposer package for integrated circuit devices
WO2008055708A2 (de) 2006-11-09 2008-05-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mikroelektronische baugruppe und verfahren zum herstellen einer mikroelektronischen baugruppe
US20120261818A1 (en) 2010-05-13 2012-10-18 Stats Chippac, Ltd. Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
WO2013004083A1 (zh) 2011-07-01 2013-01-10 中国科学院微电子研究所 一种基于柔性基板封装的屏蔽结构及其制作工艺

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US20190198411A1 (en) 2019-06-27
US11309224B2 (en) 2022-04-19
JP2019117909A (ja) 2019-07-18

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