JP6995136B2 - 周波数混雑を低減するためのフォールト・トレラント量子コンピューティングにおける物理パラメータの最適化 - Google Patents
周波数混雑を低減するためのフォールト・トレラント量子コンピューティングにおける物理パラメータの最適化 Download PDFInfo
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Description
本発明は、米国陸軍によって授与された契約番号W911NF-16-1-0114に従って、政府の支援を受けてなされたものである。米国政府は、本発明に対して一定の権利を有している。
102,104 セグメント
200 Zパリティ・チェックを実施する回路
300 Xパリティ・チェックを実施する回路
400 量子エラー訂正回路
402 制御キュービット
404 ターゲット・キュービット
406 アダマール・ゲート
408 測定デバイス
420 CNOTゲート
452 符号キュービット
454 シンドローム・キュービット
460 タイムライン
Claims (10)
- 量子エラー訂正のための回路であって、前記回路は、
ターゲット・キュービットとして構成された符号キュービットであって、第1のデフェージング時間および第1の非調和性を有する、前記符号キュービットと、
制御キュービットとして構成されたシンドローム・キュービットであって、第2のデフェージング時間および第2の非調和性を有する、前記シンドローム・キュービットと、を備え、前記ターゲット・キュービットおよび前記制御キュービットは、1つまたは複数の制御NOT(CNOT)ゲートを形成するように構成され、前記第1のデフェージング時間は前記第2のデフェージング時間よりも長く、前記第2の非調和性は前記第1の非調和性よりも高い、回路。 - 前記シンドローム・キュービットのうちの1つのシンドローム・キュービットは、前記符号キュービットのうちの4つに結合されるように構成される、請求項1に記載の回路。
- バス・レゾネータが、前記符号キュービットのうちの2つの符号キュービットと、前記シンドローム・キュービットのうちの2つのシンドローム・キュービットとを含むように構成される、請求項1に記載の回路。
- 前記2つの符号キュービットは、互いに結合されるように構成される、請求項3に記載の回路。
- 前記2つのシンドローム・キュービットは、前記2つの符号キュービットに結合されるように構成される、請求項4に記載の回路。
- 前記第1のデフェージング時間は、前記符号キュービットが所与の状態の重ね合わせを維持する時間の長さであり、前記第2のデフェージング時間は、前記シンドローム・キュービットが所与の状態の重ね合わせを維持する時間の長さである、請求項1に記載の回路。
- 前記第1の非調和性は、前記符号キュービットが調和振動子であることから逸脱していることを表し、前記第2の非調和性は、前記シンドローム・キュービットが調和振動子であることから逸脱していることを表す、請求項1に記載の回路。
- 前記符号キュービットはトランスモン・キュービットである、請求項1に記載の回路。
- 前記シンドローム・キュービットの各々は、コンデンサによってシャントされたジョセフソン接合のループであり、前記ループは3つ以上のジョセフソン接合を有する、請求項1に記載の回路。
- 量子エラー訂正のための回路を構成する方法であって、前記方法は、
符号キュービットをターゲット・キュービットとして構成することであって、前記符号キュービットは、第1のデフェージング時間および第1の非調和性を有する、前記構成することと、
シンドローム・キュービットを制御キュービットとして構成することであって、前記シンドローム・キュービットは、第2のデフェージング時間および第2の非調和性を有する、前記構成することと、を含み、前記ターゲット・キュービットおよび前記制御キュービットは、1つまたは複数の制御NOT(CNOT)ゲートを形成するように構成され、前記第1のデフェージング時間は前記第2のデフェージング時間よりも長く、前記第2の非調和性は前記第1の非調和性よりも高い、方法。
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US20180285761A1 (en) | 2018-10-04 |
CN110494870A (zh) | 2019-11-22 |
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