JP7335302B2 - 周波数混雑を低減するためのフォールト・トレラント量子コンピューティングにおける物理パラメータの最適化 - Google Patents
周波数混雑を低減するためのフォールト・トレラント量子コンピューティングにおける物理パラメータの最適化 Download PDFInfo
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Description
本発明は、米国陸軍によって授与された契約番号W911NF-16-1-0114に従って、政府の支援を受けてなされたものである。米国政府は、本発明に対して一定の権利を有している。
102,104 セグメント
200 Zパリティ・チェックを実施する回路
300 Xパリティ・チェックを実施する回路
400 量子エラー訂正回路
402 制御キュービット
404 ターゲット・キュービット
406 アダマール・ゲート
408 測定デバイス
420 CNOTゲート
452 符号キュービット
454 シンドローム・キュービット
460 タイムライン
Claims (5)
- 量子エラー訂正回路であって、
シンドローム・キュービットと、
制御NOT(CNOT)ゲートを形成するように前記シンドローム・キュービットにそれぞれが結合された符号キュービットと
を備え、
前記符号キュービットの各々はターゲット・キュービットであり、前記シンドローム・キュービットは制御キュービットであり、前記シンドローム・キュービットはパリティを取得するために測定され、
前記シンドローム・キュービットは高非調和性キュービットであり、前記シンドローム・キュービットの非調和性は前記符号キュービットの非調和性よりも高い、
量子エラー訂正回路。 - 前記符号キュービットは互いに結合されない、請求項1に記載の量子エラー訂正回路。
- 前記シンドローム・キュービットは固定状態にある、請求項1に記載の量子エラー訂正回路。
- 前記符号キュービットは重ね合わせ状態にある、請求項1に記載の量子エラー訂正回路。
- 量子エラー訂正回路を構成する方法であって、前記方法は、
シンドローム・キュービットを設けることと、
制御NOT(CNOT)ゲートを形成するように前記シンドローム・キュービットにそれぞれが結合された符号キュービットを設けることと、
を含み、
前記符号キュービットの各々はターゲット・キュービットであり、前記シンドローム・キュービットは制御キュービットであり、前記シンドローム・キュービットはパリティを取得するために測定されるように構成され、
前記シンドローム・キュービットは高非調和性キュービットであり、前記シンドローム・キュービットの非調和性は前記符号キュービットの非調和性よりも高い、
方法。
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US15/473,011 US9978020B1 (en) | 2017-03-29 | 2017-03-29 | Optimizing physical parameters in fault-tolerant quantum computing to reduce frequency crowding |
US15/473,011 | 2017-03-29 | ||
JP2019553105A JP6995136B2 (ja) | 2017-03-29 | 2017-12-05 | 周波数混雑を低減するためのフォールト・トレラント量子コンピューティングにおける物理パラメータの最適化 |
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JP2021157304A Active JP7335302B2 (ja) | 2017-03-29 | 2021-09-27 | 周波数混雑を低減するためのフォールト・トレラント量子コンピューティングにおける物理パラメータの最適化 |
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JP2020515970A (ja) | 2020-05-28 |
US9978020B1 (en) | 2018-05-22 |
US20180285761A1 (en) | 2018-10-04 |
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