JP6890271B2 - 半導体装置およびその製造方法 - Google Patents
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- 230000007261 regionalization Effects 0.000 description 1
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Description
本開示の実施形態を説明する前に、本開示の基礎となった知見を説明する。
半導体基板と、
前記半導体基板の上に形成された半導体層であって、前記半導体基板と反対側の表面部分に複数のウェル領域を有し、前記複数のウェル領域のそれぞれは、ソース領域を含み、前記複数のウェル領域外ではドリフト領域を有し、前記半導体基板と反対側の表面に無効化領域を有する半導体層と、
前記半導体層の上に形成されたゲート絶縁層であって、前記無効化領域内外の両方において、前記複数のウェル領域のソース領域の少なくとも一部を露出するゲート絶縁層と、
前記無効化領域外において、前記ゲート絶縁層の上に形成され、前記無効化領域内において、前記ゲート絶縁層の上に形成されないゲート電極と、
前記無効化領域外において、前記ゲート電極を覆い、前記無効化領域内において、前記ゲート絶縁層の少なくとも一部を覆う絶縁膜と、
前記無効化領域内外の両方において、前記絶縁膜を覆い、前記複数のウェル領域の、露出されたソース領域と接触するソース配線と、
を備える半導体装置。
前記無効化領域内において、前記ゲート絶縁層の上下および内部の少なくとも1箇所に、導電性または非導電性の異物が存在する、項目1に記載の半導体装置。
半導体基板と、
前記半導体基板の上に形成された半導体層であって、前記半導体基板と反対側の表面部分に複数のウェル領域を有し、前記複数のウェル領域のそれぞれは、ソース領域を含み、前記複数のウェル領域外ではドリフト領域を有し、前記半導体基板と反対側の表面に無効化領域を有する半導体層と、
前記半導体層の上に形成されたゲート絶縁層であって、前記無効化領域外において、前記複数のウェル領域のソース領域の少なくとも一部を露出し、前記無効化領域内において、前記複数のウェル領域のソース領域を露出しないゲート絶縁層と、
前記無効化領域内外の両方において、前記ゲート絶縁層の上に形成されたゲート電極と、
前記無効化領域外において、前記ゲート電極を覆い、前記無効化領域内において、前記ゲート電極と、前記ゲート絶縁層の少なくとも一部とを覆う絶縁膜と、
前記無効化領域内外の両方において、前記絶縁膜を覆うソース配線であって、前記無効化領域外において、前記複数のウェル領域の、露出されたソース領域と接触するソース配線と、
を備える半導体装置。
前記無効化領域内において、前記ゲート絶縁層の上下および内部の少なくとも1箇所に、導電性または非導電性の異物が存在する、項目3に記載の半導体装置。
前記無効化領域内において、前記ゲート電極は、前記複数のウェル領域のソース領域の少なくとも一部と、前記ゲート絶縁層を介して重なる、項目3または4に記載の半導体装置。
半導体基板と、前記半導体基板の上に形成された半導体層であって、前記半導体基板と反対側の表面部分に複数のウェル領域を有し、複数のウェル領域のそれぞれは、ソース領域を含み、前記複数のウェル領域外ではドリフト領域を有する半導体層と、前記半導体層の上に形成されたゲート絶縁層と、前記ゲート絶縁層の上に形成されたゲート電極と、を用意する第1の工程と、
前記ゲート電極の、前記複数のウェル領域のソース領域と重なる部分を除去する第2の工程と、
前記第1または第2の工程において生じた欠陥を検査し、前記欠陥の座標を記録し、前記欠陥の座標に基づいて、無効化領域を決定する第3の工程と、
前記無効化領域内において、前記ゲート電極を除去する第4の工程と、
前記無効化領域外において、前記ゲート電極の上に絶縁膜を形成し、前記無効化領域内において、前記ゲート絶縁層の少なくとも一部の上に絶縁膜を形成し、前記無効化領域内外の両方において、前記複数のウェル領域のソース領域の少なくとも一部を露出するソースコンタクトホールを前記絶縁膜に形成する第5の工程と、
前記無効化領域内外の両方において、前記絶縁膜を覆い、前記ソースコンタクトホールを通して、前記複数のウェル領域の、露出されたソース領域と接触するソース配線を形成する第6の工程と、
を包含する半導体装置の製造方法。
半導体基板と、前記半導体基板の上に形成された半導体層であって、前記半導体基板と反対側の表面部分に複数のウェル領域を有し、複数のウェル領域のそれぞれは、ソース領域を含み、前記複数のウェル領域外ではドリフト領域を有する半導体層と、前記半導体層の上に形成されたゲート絶縁層と、前記ゲート絶縁層の上に形成されたゲート電極と、を用意する第1の工程と、
前記ゲート電極の、前記複数のウェル領域のソース領域と重なる部分を除去する第2の工程と、
前記第1または第2の工程において生じた欠陥を検査し、前記欠陥の座標を記録し、前記欠陥の座標に基づいて、無効化領域を決定する第3の工程と、
前記無効化領域内外の両方において、前記ゲート絶縁層と、前記第2の工程において形成された前記ゲート電極とを、絶縁膜で覆い、前記無効化領域外において、前記複数のウェル領域のソース領域の少なくとも一部を露出するソースコンタクトホールを前記絶縁膜に形成し、前記無効化領域内において、前記複数のウェル領域のソース領域を露出するソースコンタクトホールを前記絶縁膜に形成しない第4の工程と、
前記無効化領域内外の両方において、前記絶縁膜を覆い、前記無効化領域外において、前記ソースコンタクトホールを通して、前記複数のウェル領域の、露出されたソース領域と接触するソース配線を形成する第5の工程と、
を包含する半導体装置の製造方法。
以下の説明では、欠陥の一例として、プロセス欠陥に注目する。
101 半導体基板
102 ドリフト領域
103 ウェル領域
105 ボディ領域
108 ソース領域
109 コンタクト領域
110 半導体層
111 ゲート絶縁層
113 ゲート電極
117 絶縁膜
118 ソース配線
121、123 導電性パーティクル、導電性または非導電性の異物
122 ゲート電極のパターン不良
130、131 レジスト
R 無効化領域
Claims (2)
- 半導体基板と、前記半導体基板の上に形成された半導体層であって、前記半導体基板と反対側の表面部分に複数のウェル領域を有し、複数のウェル領域のそれぞれは、ソース領域を含み、前記複数のウェル領域外ではドリフト領域を有する半導体層と、前記半導体層の上に形成されたゲート絶縁層と、前記ゲート絶縁層の上に形成されたゲート電極と、を用意する第1の工程と、
前記ゲート電極の、前記複数のウェル領域のソース領域と重なる部分を除去する第2の工程と、
前記第1または第2の工程において生じた欠陥を検査し、前記欠陥の座標を記録し、前記欠陥の座標に基づいて、無効化領域を決定する第3の工程と、
前記ゲート絶縁層および前記ゲート電極をレジストで覆い、前記無効化領域内において、レーザ加工によって前記レジストを除去した後、前記無効化領域内において、前記ゲート電極を除去する第4の工程と、
前記無効化領域外において、前記ゲート電極の上に絶縁膜を形成し、前記無効化領域内において、前記ゲート絶縁層の少なくとも一部の上に絶縁膜を形成し、前記無効化領域内外の両方において、前記複数のウェル領域のソース領域の少なくとも一部を露出するソースコンタクトホールを前記絶縁膜に形成する第5の工程と、
前記無効化領域内外の両方において、前記絶縁膜を覆い、前記ソースコンタクトホールを通して、前記複数のウェル領域の、露出されたソース領域と接触するソース配線を形成する第6の工程と、
を包含する半導体装置の製造方法。 - 半導体基板と、前記半導体基板の上に形成された半導体層であって、前記半導体基板と反対側の表面部分に複数のウェル領域を有し、複数のウェル領域のそれぞれは、ソース領域を含み、前記複数のウェル領域外ではドリフト領域を有する半導体層と、前記半導体層の上に形成されたゲート絶縁層と、前記ゲート絶縁層の上に形成されたゲート電極と、を用意する第1の工程と、
前記ゲート電極の、前記複数のウェル領域のソース領域と重なる部分を除去する第2の工程と、
前記第1または第2の工程において生じた欠陥を検査し、前記欠陥の座標を記録し、前記欠陥の座標に基づいて、無効化領域を決定する第3の工程と、
前記無効化領域内外の両方において、前記ゲート絶縁層と、前記第2の工程において形成された前記ゲート電極とを、絶縁膜で覆い、前記絶縁膜上にレジストを形成し、前記レジストに、ソースコンタクトホール用のパターンを形成し、前記無効化領域内において、ディスペンサを用いて他のレジストをさらに形成し、前記無効化領域外において、エッチングを行うことにより、前記複数のウェル領域のソース領域の少なくとも一部を露出するソースコンタクトホールを前記絶縁膜に形成し、前記無効化領域内において、前記複数のウェル領域のソース領域を露出するソースコンタクトホールを前記絶縁膜に形成しない第4の工程と、
前記無効化領域内外の両方において、前記絶縁膜を覆い、前記無効化領域外において、前記ソースコンタクトホールを通して、前記複数のウェル領域の、露出されたソース領域と接触するソース配線を形成する第5の工程と、
を包含する半導体装置の製造方法。
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