JP6876681B2 - ３相インターフェース用の多相クロックデータ復元 - Google Patents

３相インターフェース用の多相クロックデータ復元 Download PDF

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Publication number
JP6876681B2
JP6876681B2 JP2018510826A JP2018510826A JP6876681B2 JP 6876681 B2 JP6876681 B2 JP 6876681B2 JP 2018510826 A JP2018510826 A JP 2018510826A JP 2018510826 A JP2018510826 A JP 2018510826A JP 6876681 B2 JP6876681 B2 JP 6876681B2
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clock signal
frequency
pulse
signal
clock
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JP2018526912A5 (enExample
JP2018526912A (ja
Inventor
イン・デュアン
チュルキュ・イ
シー−ウェイ・チョウ
ハリー・ダン
オージョン・クウォン
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2018510826A 2015-09-01 2016-08-09 ３相インターフェース用の多相クロックデータ復元 Active JP6876681B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/842,644 US9496879B1 (en) 2015-09-01 2015-09-01 Multiphase clock data recovery for a 3-phase interface
US14/842,644 2015-09-01
PCT/US2016/046211 WO2017039985A1 (en) 2015-09-01 2016-08-09 Multiphase clock data recovery for a 3-phase interface

Publications (3)

Publication Number Publication Date
JP2018526912A JP2018526912A (ja) 2018-09-13
JP2018526912A5 JP2018526912A5 (enExample) 2019-09-05
JP6876681B2 true JP6876681B2 (ja) 2021-05-26

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ID=56694265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018510826A Active JP6876681B2 (ja) 2015-09-01 2016-08-09 ３相インターフェース用の多相クロックデータ復元

Country Status (10)

Country Link
US (1) US9496879B1 (enExample)
EP (1) EP3345334B1 (enExample)
JP (1) JP6876681B2 (enExample)
KR (1) KR102522742B1 (enExample)
CN (1) CN107925563B (enExample)
BR (1) BR112018004159B1 (enExample)
CA (1) CA2992751C (enExample)
ES (1) ES2777373T3 (enExample)
TW (1) TWI720008B (enExample)
WO (1) WO2017039985A1 (enExample)

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US9711041B2 (en) 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
KR20170008076A (ko) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템
US9485080B1 (en) * 2015-09-01 2016-11-01 Qualcomm Incorporated Multiphase clock data recovery circuit calibration
US10742390B2 (en) * 2016-07-13 2020-08-11 Novatek Microelectronics Corp. Method of improving clock recovery and related device
US10419246B2 (en) * 2016-08-31 2019-09-17 Qualcomm Incorporated C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration
US10284361B2 (en) * 2017-05-05 2019-05-07 Mediatek Inc. Channel skew calibration method and associated receiver and system
KR101899247B1 (ko) * 2017-05-31 2018-09-14 한양대학교 산학협력단 동시 스위칭 잡음을 제거하는 송신기 및 이에 있어서 데이터 전송 방법
KR102401996B1 (ko) 2018-05-28 2022-05-24 삼성전자주식회사 타이밍 조절이 가능한 고속 멀티 레벨 신호 수신기를 포함하는 반도체 장치 및 상기 수신기를 포함하는 반도체 테스트 장치
US10469214B1 (en) 2018-12-13 2019-11-05 Intel Corporation Clock recovery circuit and method of operating same
US10581587B1 (en) * 2019-04-29 2020-03-03 Advanced Micro Devices, Inc. Deskewing method for a physical layer interface on a multi-chip module
CN112422256B (zh) * 2019-08-23 2023-12-05 微芯片技术股份有限公司 数字时钟和数据恢复的快速初始相位搜索的装置和方法
US11095425B2 (en) * 2019-10-25 2021-08-17 Qualcomm Incorporated Small loop delay clock and data recovery block for high-speed next generation C-PHY
US11038666B1 (en) 2019-12-11 2021-06-15 Qualcomm Incorporated Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces
KR20210088808A (ko) 2020-01-06 2021-07-15 삼성전자주식회사 전자 장치 및 전자 장치의 동작 방법
KR20210088807A (ko) * 2020-01-06 2021-07-15 삼성전자주식회사 전자 장치 및 전자 장치의 동작 방법
US11031939B1 (en) * 2020-03-19 2021-06-08 Mellanox Technologies, Ltd. Phase detector command propagation between lanes in MCM USR serdes
US11349445B2 (en) * 2020-09-10 2022-05-31 Qualcomm Incorporated Compensation of common mode voltage drop of sensing amplifier output due to decision feedback equalizer (DFE) taps
KR102265187B1 (ko) * 2021-02-08 2021-06-16 슈가스 주식회사 클럭 복구 회로
JP2022146532A (ja) 2021-03-22 2022-10-05 キオクシア株式会社 メモリシステム及び遅延制御方法
US11520729B2 (en) 2021-05-04 2022-12-06 Qualcomm Incorporated I2C bus architecture using shared clock and dedicated data lines
US11545980B1 (en) 2021-09-08 2023-01-03 Qualcomm Incorporated Clock and data recovery for multi-phase, multi-level encoding
CN113886300B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种总线接口的时钟数据自适应恢复系统及芯片
US11956342B2 (en) 2021-12-27 2024-04-09 Nvidia Corporation Reliable link management for a high-speed signaling interconnect
CN114298075B (zh) * 2021-12-30 2024-02-06 江苏集萃智能集成电路设计技术研究所有限公司 基于mcu的超高频国标阅读器基带解码方法
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Also Published As

Publication number Publication date
CA2992751A1 (en) 2017-03-09
BR112018004159A2 (pt) 2018-10-02
US9496879B1 (en) 2016-11-15
KR102522742B1 (ko) 2023-04-17
CN107925563B (zh) 2020-12-08
WO2017039985A1 (en) 2017-03-09
TWI720008B (zh) 2021-03-01
EP3345334A1 (en) 2018-07-11
CN107925563A (zh) 2018-04-17
KR20180048952A (ko) 2018-05-10
BR112018004159B1 (pt) 2023-12-05
ES2777373T3 (es) 2020-08-04
CA2992751C (en) 2024-01-09
TW201714425A (zh) 2017-04-16
EP3345334B1 (en) 2019-11-20
JP2018526912A (ja) 2018-09-13

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