JP6847863B2 - パッケージオンパッケージ構造体用のインターポーザ - Google Patents

パッケージオンパッケージ構造体用のインターポーザ Download PDF

Info

Publication number
JP6847863B2
JP6847863B2 JP2017563204A JP2017563204A JP6847863B2 JP 6847863 B2 JP6847863 B2 JP 6847863B2 JP 2017563204 A JP2017563204 A JP 2017563204A JP 2017563204 A JP2017563204 A JP 2017563204A JP 6847863 B2 JP6847863 B2 JP 6847863B2
Authority
JP
Japan
Prior art keywords
die
mold
interposer
package
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017563204A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018518057A (ja
Inventor
ジェ・シク・イ
キュ−ピョン・ファン
ホン・ボク・ウィ
Original Assignee
クアルコム,インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム,インコーポレイテッド filed Critical クアルコム,インコーポレイテッド
Publication of JP2018518057A publication Critical patent/JP2018518057A/ja
Application granted granted Critical
Publication of JP6847863B2 publication Critical patent/JP6847863B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66Conductive materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69Insulating materials thereof
    • H10W70/698Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/016Manufacture or treatment using moulds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/401Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07202Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207Temporary substrates, e.g. removable substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/823Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/877Bump connectors and die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2017563204A 2015-06-08 2016-05-24 パッケージオンパッケージ構造体用のインターポーザ Active JP6847863B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/733,201 US9613942B2 (en) 2015-06-08 2015-06-08 Interposer for a package-on-package structure
US14/733,201 2015-06-08
PCT/US2016/033948 WO2016200604A1 (en) 2015-06-08 2016-05-24 Interposer for a package-on-package structure

Publications (2)

Publication Number Publication Date
JP2018518057A JP2018518057A (ja) 2018-07-05
JP6847863B2 true JP6847863B2 (ja) 2021-03-24

Family

ID=56119766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017563204A Active JP6847863B2 (ja) 2015-06-08 2016-05-24 パッケージオンパッケージ構造体用のインターポーザ

Country Status (8)

Country Link
US (1) US9613942B2 (https=)
EP (2) EP4546409A3 (https=)
JP (1) JP6847863B2 (https=)
KR (1) KR102550873B1 (https=)
CN (1) CN107690700B (https=)
BR (1) BR112017026386B1 (https=)
CA (1) CA2985197C (https=)
WO (1) WO2016200604A1 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108353505B (zh) * 2015-11-13 2021-11-30 英特尔公司 包括衬底桥的电子组件
US20170262398A1 (en) * 2016-03-08 2017-09-14 L3 Technologies Inc. Power Efficient Distributed Beam Forming Architecture Using Interconnected Processing Nodes
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
WO2018125080A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Enabling long interconnect bridges
KR20180124256A (ko) 2017-05-11 2018-11-21 에스케이하이닉스 주식회사 몰드비아를 갖는 적층 반도체 패키지 및 그의 제조방법
US11498096B2 (en) 2018-11-06 2022-11-15 Siemens Medical Solutions Usa, Inc. Chip-on-array with interposer for a multidimensional transducer array
KR102538704B1 (ko) * 2018-12-04 2023-06-01 에스케이하이닉스 주식회사 플렉시블 브리지 다이를 포함한 스택 패키지
US11798865B2 (en) 2019-03-04 2023-10-24 Intel Corporation Nested architectures for enhanced heterogeneous integration
US10818640B1 (en) * 2019-04-02 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Die stacks and methods forming same
KR102674087B1 (ko) * 2019-09-06 2024-06-12 에스케이하이닉스 주식회사 전자기간섭 차폐층을 포함하는 반도체 패키지
US11018113B2 (en) * 2019-10-17 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory module, semiconductor package including the same, and manufacturing method thereof
DE102020119181A1 (de) * 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterpackages und verfahren zu deren herstellung
US11302643B2 (en) 2020-03-25 2022-04-12 Intel Corporation Microelectronic component having molded regions with through-mold vias
KR102875889B1 (ko) * 2021-05-06 2025-10-24 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CN118525369A (zh) * 2022-02-28 2024-08-20 株式会社力森诺科 底部填充材料、半导体封装和半导体封装的制造方法
US20230395578A1 (en) * 2022-06-06 2023-12-07 Intel Corporation Memory package on extended base die over soc die for package layer count and form factor reduction
US20250029951A1 (en) * 2023-07-18 2025-01-23 Advanced Semiconductor Engineering, Inc. Electronic device
US20260076254A1 (en) * 2024-09-06 2026-03-12 Qualcomm Incorporated Ultra low profile rdl package-on-package

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7151010B2 (en) 2004-12-01 2006-12-19 Kyocera Wireless Corp. Methods for assembling a stack package for high density integrated circuits
US8089143B2 (en) * 2005-02-10 2012-01-03 Stats Chippac Ltd. Integrated circuit package system using interposer
US7901987B2 (en) 2008-03-19 2011-03-08 Stats Chippac Ltd. Package-on-package system with internal stacking module interposer
US8106520B2 (en) 2008-09-11 2012-01-31 Micron Technology, Inc. Signal delivery in stacked device
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US20120319293A1 (en) * 2011-06-17 2012-12-20 Bok Eng Cheah Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package
JP2013030593A (ja) * 2011-07-28 2013-02-07 J Devices:Kk 半導体装置、該半導体装置を垂直に積層した半導体モジュール構造及びその製造方法
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8704384B2 (en) 2012-02-17 2014-04-22 Xilinx, Inc. Stacked die assembly
US9263412B2 (en) * 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US20140089609A1 (en) 2012-09-26 2014-03-27 Advanced Micro Devices, Inc. Interposer having embedded memory controller circuitry
US9391041B2 (en) * 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8957525B2 (en) 2012-12-06 2015-02-17 Texas Instruments Incorporated 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US9461025B2 (en) * 2013-03-12 2016-10-04 Taiwan Semiconductor Manfacturing Company, Ltd. Electric magnetic shielding structure in packages
US8901748B2 (en) 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US9768048B2 (en) 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure
US20140339705A1 (en) * 2013-05-17 2014-11-20 Nvidia Corporation Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias
WO2014209330A1 (en) * 2013-06-27 2014-12-31 Intel IP Corporation High conductivity high frequency via for electronic systems
WO2015047330A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Die package with superposer substrate for passive components
US9396300B2 (en) * 2014-01-16 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof
US10026671B2 (en) * 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US20150303172A1 (en) * 2014-04-22 2015-10-22 Broadcom Corporation Reconstitution techniques for semiconductor packages

Also Published As

Publication number Publication date
CA2985197A1 (en) 2016-12-15
US20160358899A1 (en) 2016-12-08
CA2985197C (en) 2023-09-26
EP4546409A2 (en) 2025-04-30
US9613942B2 (en) 2017-04-04
CN107690700B (zh) 2022-01-11
CN107690700A (zh) 2018-02-13
BR112017026386B1 (pt) 2023-02-07
KR102550873B1 (ko) 2023-07-03
JP2018518057A (ja) 2018-07-05
EP3304593A1 (en) 2018-04-11
WO2016200604A1 (en) 2016-12-15
KR20180016384A (ko) 2018-02-14
EP4546409A3 (en) 2025-07-09
BR112017026386A2 (https=) 2018-08-21

Similar Documents

Publication Publication Date Title
JP6847863B2 (ja) パッケージオンパッケージ構造体用のインターポーザ
EP3772098B1 (en) Multi-die ultrafine pitch patch architecture and method of making
JP5698246B2 (ja) チップ識別構造体を有する垂直積層可能なダイ
TWI625830B (zh) 具有一被動微電子裝置設置於一封裝體中的微電子封裝技術
CN107851588B (zh) 包括多个管芯的堆叠式封装(pop)结构
TW202101702A (zh) 基板補片重構選項
CN107004612B (zh) 在基板与管芯之间包括光敏填料的集成器件封装
CN109994435A (zh) 桥接器中枢拼接架构
CN107636813A (zh) 具有高密度管芯至管芯连接的半导体封装及其制造方法
TW202123411A (zh) 用於積體電路封裝體之複合式橋接晶粒至晶粒互連件
US11594491B2 (en) Multi-die interconnect
TW202220136A (zh) 混合焊盤尺寸和焊盤設計
US20160225748A1 (en) Package-on-package (pop) structure
TW202008522A (zh) 半導體封裝
TWI601217B (zh) 包含積體電路(ic)封裝體之間的可撓連接件的積體裝置
TWI918920B (zh) 多晶粒互連
US20250112164A1 (en) Controlling substrate bump height
Garrou et al. 3d ic integration since 2008
CA2990470C (en) Package-on-package (pop) structure including multiple dies

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171211

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190510

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200803

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201104

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210201

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210303

R150 Certificate of patent or registration of utility model

Ref document number: 6847863

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250