JP6808282B2 - インターポーザの製造方法 - Google Patents

インターポーザの製造方法 Download PDF

Info

Publication number
JP6808282B2
JP6808282B2 JP2016242236A JP2016242236A JP6808282B2 JP 6808282 B2 JP6808282 B2 JP 6808282B2 JP 2016242236 A JP2016242236 A JP 2016242236A JP 2016242236 A JP2016242236 A JP 2016242236A JP 6808282 B2 JP6808282 B2 JP 6808282B2
Authority
JP
Japan
Prior art keywords
glass substrate
interposer
laminated body
cutting groove
forming step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016242236A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018098379A (ja
Inventor
鈴木 克彦
克彦 鈴木
陽平 山下
陽平 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Priority to JP2016242236A priority Critical patent/JP6808282B2/ja
Priority to TW106138540A priority patent/TWI743244B/zh
Priority to KR1020170166942A priority patent/KR20180068862A/ko
Priority to CN201711282902.9A priority patent/CN108231570A/zh
Publication of JP2018098379A publication Critical patent/JP2018098379A/ja
Application granted granted Critical
Publication of JP6808282B2 publication Critical patent/JP6808282B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/38Removing material by boring or cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Laser Beam Processing (AREA)
  • Re-Forming, After-Treatment, Cutting And Transporting Of Glass Products (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
JP2016242236A 2016-12-14 2016-12-14 インターポーザの製造方法 Active JP6808282B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2016242236A JP6808282B2 (ja) 2016-12-14 2016-12-14 インターポーザの製造方法
TW106138540A TWI743244B (zh) 2016-12-14 2017-11-08 中介載板的製造方法
KR1020170166942A KR20180068862A (ko) 2016-12-14 2017-12-06 인터포저의 제조 방법
CN201711282902.9A CN108231570A (zh) 2016-12-14 2017-12-07 中介层的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016242236A JP6808282B2 (ja) 2016-12-14 2016-12-14 インターポーザの製造方法

Publications (2)

Publication Number Publication Date
JP2018098379A JP2018098379A (ja) 2018-06-21
JP6808282B2 true JP6808282B2 (ja) 2021-01-06

Family

ID=62633129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016242236A Active JP6808282B2 (ja) 2016-12-14 2016-12-14 インターポーザの製造方法

Country Status (4)

Country Link
JP (1) JP6808282B2 (zh)
KR (1) KR20180068862A (zh)
CN (1) CN108231570A (zh)
TW (1) TWI743244B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7164411B2 (ja) * 2018-11-15 2022-11-01 株式会社ディスコ 積層体の加工方法
JP7164412B2 (ja) * 2018-11-16 2022-11-01 株式会社ディスコ 積層体の加工方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617681B1 (en) 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
JP2005012203A (ja) * 2003-05-29 2005-01-13 Hamamatsu Photonics Kk レーザ加工方法
JP5352624B2 (ja) * 2005-11-10 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5608521B2 (ja) * 2010-11-26 2014-10-15 新光電気工業株式会社 半導体ウエハの分割方法と半導体チップ及び半導体装置
JP6151557B2 (ja) * 2013-05-13 2017-06-21 株式会社ディスコ レーザー加工方法
JP6246534B2 (ja) * 2013-09-11 2017-12-13 株式会社ディスコ ウエーハの加工方法
JP2015198212A (ja) 2014-04-03 2015-11-09 凸版印刷株式会社 ガラスインターポーザ
JP2015207580A (ja) * 2014-04-17 2015-11-19 凸版印刷株式会社 配線基板およびその製造方法

Also Published As

Publication number Publication date
TW201826455A (zh) 2018-07-16
TWI743244B (zh) 2021-10-21
JP2018098379A (ja) 2018-06-21
CN108231570A (zh) 2018-06-29
KR20180068862A (ko) 2018-06-22

Similar Documents

Publication Publication Date Title
JP6779574B2 (ja) インターポーザの製造方法
TWI756437B (zh) 玻璃中介層之製造方法
JP3795040B2 (ja) 半導体装置の製造方法
KR102349663B1 (ko) 웨이퍼의 가공 방법
JP2015207604A (ja) ウェーハの加工方法
TWI824139B (zh) 層積晶圓之加工方法
JP2013197108A (ja) ウエーハのレーザー加工方法
JP6808282B2 (ja) インターポーザの製造方法
JP2011210915A (ja) 単結晶基板の切断装置、および単結晶基板の切断方法
JP6012185B2 (ja) 半導体デバイスの製造方法
US20180308711A1 (en) Workpiece processing method
JP5453123B2 (ja) 切削方法
JP6981800B2 (ja) 積層型素子の製造方法
JP5969214B2 (ja) 半導体デバイスの製造方法
JP6925902B2 (ja) 積層型素子の製造方法
TW201923860A (zh) 層疊型元件的製造方法
JP7223828B2 (ja) 積層型素子の製造方法
JP2013157449A (ja) 半導体デバイスの製造方法
JP6440558B2 (ja) 被加工物の加工方法
JP2022024591A (ja) ウェーハ加工方法及びシステム
JP2013157455A (ja) 半導体デバイスの製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191018

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200813

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200818

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200925

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20201208

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20201208

R150 Certificate of patent or registration of utility model

Ref document number: 6808282

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250