JP6783648B2 - 配線基板、半導体装置 - Google Patents

配線基板、半導体装置 Download PDF

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Publication number
JP6783648B2
JP6783648B2 JP2016251599A JP2016251599A JP6783648B2 JP 6783648 B2 JP6783648 B2 JP 6783648B2 JP 2016251599 A JP2016251599 A JP 2016251599A JP 2016251599 A JP2016251599 A JP 2016251599A JP 6783648 B2 JP6783648 B2 JP 6783648B2
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Japan
Prior art keywords
region
pad
pads
dummy
wiring board
Prior art date
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Active
Application number
JP2016251599A
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English (en)
Japanese (ja)
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JP2018107267A (ja
JP2018107267A5 (enExample
Inventor
今藤　桂
桂 今藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2016251599A priority Critical patent/JP6783648B2/ja
Priority to US15/819,310 priority patent/US10438883B2/en
Publication of JP2018107267A publication Critical patent/JP2018107267A/ja
Publication of JP2018107267A5 publication Critical patent/JP2018107267A5/ja
Application granted granted Critical
Publication of JP6783648B2 publication Critical patent/JP6783648B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2016251599A 2016-12-26 2016-12-26 配線基板、半導体装置 Active JP6783648B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016251599A JP6783648B2 (ja) 2016-12-26 2016-12-26 配線基板、半導体装置
US15/819,310 US10438883B2 (en) 2016-12-26 2017-11-21 Wiring board and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016251599A JP6783648B2 (ja) 2016-12-26 2016-12-26 配線基板、半導体装置

Publications (3)

Publication Number Publication Date
JP2018107267A JP2018107267A (ja) 2018-07-05
JP2018107267A5 JP2018107267A5 (enExample) 2019-06-27
JP6783648B2 true JP6783648B2 (ja) 2020-11-11

Family

ID=62625891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016251599A Active JP6783648B2 (ja) 2016-12-26 2016-12-26 配線基板、半導体装置

Country Status (2)

Country Link
US (1) US10438883B2 (enExample)
JP (1) JP6783648B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7353113B2 (ja) * 2019-09-27 2023-09-29 日本電波工業株式会社 電子部品及び電子部品の製造方法
US12027493B2 (en) * 2019-11-04 2024-07-02 Xilinx, Inc. Fanout integration for stacked silicon package assembly
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
KR102910880B1 (ko) 2020-09-08 2026-01-14 삼성전자주식회사 반도체 패키지
CN112382618B (zh) * 2020-11-09 2023-10-27 成都海光集成电路设计有限公司 一种封装结构及封装方法
KR102932179B1 (ko) 2021-07-22 2026-03-04 삼성전자주식회사 반도체 패키지
US11997842B2 (en) * 2021-08-31 2024-05-28 Taiwan Semiconductor Manufacturing Company Limited Dummy metal bonding pads for underfill application in semiconductor die packaging and methods of forming the same
CN114488632B (zh) * 2022-01-27 2023-06-20 武汉天马微电子有限公司 一种显示面板、显示装置及其检测方法
JP2025008730A (ja) * 2023-07-06 2025-01-20 日本特殊陶業株式会社 配線基板
EP4521859A4 (en) * 2023-07-07 2026-07-08 Samsung Electronics Co Ltd PRINTED CIRCUIT BOARD ASSEMBLY AND ITS MANUFACTURING PROCESS

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3596807B2 (ja) * 2000-08-09 2004-12-02 インターナショナル・ビジネス・マシーンズ・コーポレーション プリント配線板及びその製造方法
JP3657246B2 (ja) * 2002-07-29 2005-06-08 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4580633B2 (ja) * 2003-11-14 2010-11-17 スタンレー電気株式会社 半導体装置及びその製造方法
JP4820683B2 (ja) * 2006-04-28 2011-11-24 川崎マイクロエレクトロニクス株式会社 半導体装置と半導体装置の絶縁破壊防止方法
US20070252252A1 (en) * 2006-04-28 2007-11-01 Powertech Technology Inc. Structure of electronic package and printed circuit board thereof
JP2008218758A (ja) * 2007-03-06 2008-09-18 Matsushita Electric Ind Co Ltd 電子回路実装構造体
JP2011029601A (ja) * 2009-06-22 2011-02-10 Mitsui Mining & Smelting Co Ltd プリント配線基板およびその製造方法
JP5595524B2 (ja) * 2010-12-28 2014-09-24 京セラ株式会社 光モジュールおよび光配線基板
JP2014183085A (ja) 2013-03-18 2014-09-29 Dainippon Printing Co Ltd マルチチップモジュール用基板、マルチチップモジュール用多層配線基板、マルチチップモジュール及びマルチチップ多層配線モジュール
US9799622B2 (en) * 2014-06-18 2017-10-24 Dyi-chung Hu High density film for IC package

Also Published As

Publication number Publication date
JP2018107267A (ja) 2018-07-05
US10438883B2 (en) 2019-10-08
US20180182701A1 (en) 2018-06-28

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