JP6768173B1 - 分散セクタを用いた行冗長性 - Google Patents

分散セクタを用いた行冗長性 Download PDF

Info

Publication number
JP6768173B1
JP6768173B1 JP2020505405A JP2020505405A JP6768173B1 JP 6768173 B1 JP6768173 B1 JP 6768173B1 JP 2020505405 A JP2020505405 A JP 2020505405A JP 2020505405 A JP2020505405 A JP 2020505405A JP 6768173 B1 JP6768173 B1 JP 6768173B1
Authority
JP
Japan
Prior art keywords
sectors
memory
sector
erase
additional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020505405A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020532036A (ja
Inventor
ダノン コビ
ダノン コビ
ベッツァー ヨラム
ベッツァー ヨラム
コトリッキ ウリ
コトリッキ ウリ
フェルドマン アリー
フェルドマン アリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Application granted granted Critical
Publication of JP6768173B1 publication Critical patent/JP6768173B1/ja
Publication of JP2020532036A publication Critical patent/JP2020532036A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/806—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by reducing size of decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/814—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for optimized yield
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2020505405A 2017-08-29 2018-08-03 分散セクタを用いた行冗長性 Active JP6768173B1 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762551314P 2017-08-29 2017-08-29
US62/551,314 2017-08-29
US15/850,779 US10141065B1 (en) 2017-08-29 2017-12-21 Row redundancy with distributed sectors
US15/850,779 2017-12-21
PCT/US2018/045223 WO2019045951A1 (en) 2017-08-29 2018-08-03 RANK REDUNDANCY WITH DISTRIBUTED SECTORS

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2020157303A Division JP7157785B2 (ja) 2017-08-29 2020-09-18 分散セクタを用いた行冗長性

Publications (2)

Publication Number Publication Date
JP6768173B1 true JP6768173B1 (ja) 2020-10-14
JP2020532036A JP2020532036A (ja) 2020-11-05

Family

ID=64315600

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2020505405A Active JP6768173B1 (ja) 2017-08-29 2018-08-03 分散セクタを用いた行冗長性
JP2020157303A Active JP7157785B2 (ja) 2017-08-29 2020-09-18 分散セクタを用いた行冗長性

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2020157303A Active JP7157785B2 (ja) 2017-08-29 2020-09-18 分散セクタを用いた行冗長性

Country Status (6)

Country Link
US (1) US10141065B1 (enExample)
JP (2) JP6768173B1 (enExample)
CN (1) CN111033628B (enExample)
DE (1) DE112018004795T5 (enExample)
TW (1) TWI676177B (enExample)
WO (1) WO2019045951A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI802971B (zh) * 2021-08-23 2023-05-21 旺宏電子股份有限公司 記憶體晶胞，記憶體裝置之製造方法及其操作方法
US12069857B2 (en) 2021-08-23 2024-08-20 Macronix International Co., Ltd. Memory cell, memory device manufacturing method and memory device operation method thereof

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996036050A1 (en) 1995-05-12 1996-11-14 Advanced Micro Devices, Inc. Sector architecture for flash memory device
US6081878A (en) * 1997-03-31 2000-06-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US5881003A (en) * 1997-07-16 1999-03-09 International Business Machines Corporation Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration
US6553510B1 (en) * 1999-09-02 2003-04-22 Micron Technology, Inc. Memory device including redundancy routine for correcting random errors
US6397313B1 (en) * 1999-10-19 2002-05-28 Advanced Micro Devices, Inc. Redundant dual bank architecture for a simultaneous operation flash memory
JP2001291395A (ja) * 2000-04-10 2001-10-19 Hitachi Ltd 半導体記憶装置
US6496425B1 (en) * 2000-08-21 2002-12-17 Micron Technology, Inc Multiple bit line column redundancy
KR100375998B1 (ko) 2000-11-17 2003-03-15 (주)실리콘세븐 자동 테스트 및 리페어 기능을 내장하는 반도체 메모리장치 및 그 방법
ITRM20010516A1 (it) 2001-08-29 2003-02-28 Micron Technology Inc Architettura a schiera di memorie flash.
US7093156B1 (en) 2002-05-13 2006-08-15 Virage Logic Corp. Embedded test and repair scheme and interface for compiling a memory assembly with redundancy implementation
EP1365419B1 (en) 2002-05-21 2008-12-31 STMicroelectronics S.r.l. Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor
US6891752B1 (en) * 2002-07-31 2005-05-10 Advanced Micro Devices System and method for erase voltage control during multiple sector erase of a flash memory device
JP2004103143A (ja) * 2002-09-11 2004-04-02 Fujitsu Ltd 冗長構成を有するメモリ回路
WO2005081260A1 (ja) 2004-02-20 2005-09-01 Spansion Llc 半導体記憶装置および半導体記憶装置の冗長方法
US8339865B2 (en) 2007-11-01 2012-12-25 Spansion Israel Ltd Non binary flash array architecture and method of operation
US7613042B2 (en) 2007-11-05 2009-11-03 Spansion Llc Decoding system capable of reducing sector select area overhead for flash memory
US7609569B2 (en) 2007-11-19 2009-10-27 International Busines Machines Corporation System and method for implementing row redundancy with reduced access time and reduced device area
US7590001B2 (en) * 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares
US8730729B2 (en) * 2009-10-15 2014-05-20 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
CN103631671B (zh) * 2013-11-19 2016-05-04 无锡众志和达数据计算股份有限公司 一种ssd存储器的数据保护方法及控制器
TWI545580B (zh) 2014-01-07 2016-08-11 群聯電子股份有限公司 隨機數產生方法、記憶體儲存裝置及控制電路
TWI529721B (zh) 2014-05-06 2016-04-11 群聯電子股份有限公司 記憶體儲存裝置、記憶體控制電路單元及電源供應方法
KR20170047447A (ko) 2015-10-22 2017-05-08 에스케이하이닉스 주식회사 반도체 메모리 장치
US9741421B1 (en) 2016-04-05 2017-08-22 Micron Technology, Inc. Refresh circuitry

Also Published As

Publication number Publication date
TWI676177B (zh) 2019-11-01
JP7157785B2 (ja) 2022-10-20
WO2019045951A1 (en) 2019-03-07
DE112018004795T5 (de) 2020-06-18
US10141065B1 (en) 2018-11-27
JP2020532036A (ja) 2020-11-05
CN111033628A (zh) 2020-04-17
CN111033628B (zh) 2022-01-14
JP2021007062A (ja) 2021-01-21
TW201921365A (zh) 2019-06-01

Similar Documents

Publication Publication Date Title
TWI605469B (zh) 具有一記憶體器件之裝置、子區塊停用電路及用於控制至一記憶體器件之存取、指示一記憶體器件中之ㄧ缺陷與擦除一記憶體器件中之記憶體之方法
US6532172B2 (en) Steering gate and bit line segmentation in non-volatile memories
US10199118B2 (en) One-time programmable (OTP) memory device for reading multiple fuse bits
JP3076195B2 (ja) 不揮発性半導体記憶装置
JP2019079586A (ja) ワードライン不良検出回路を含むメモリ装置及びその駆動方法
US20180211707A1 (en) Semiconductor memory device and method of controlling semiconductor memory device
JP2006114137A (ja) 半導体記憶装置
JP4606694B2 (ja) 同時動作フラッシュメモリ用デュアルポートｃａｍ
US8947913B1 (en) Circuits and methods having programmable impedance elements
US6772273B1 (en) Block-level read while write method and apparatus
KR100491912B1 (ko) 불휘발성 반도체 메모리
US7551510B2 (en) Memory block reallocation in a flash memory device
JP7157785B2 (ja) 分散セクタを用いた行冗長性
US11749370B2 (en) Method of testing a memory circuit and memory circuit
JP4757978B2 (ja) 不揮発性メモリ装置
JP2009146548A (ja) 不揮発性半導体記憶装置
JPWO2005081260A1 (ja) 半導体記憶装置および半導体記憶装置の冗長方法
TWI763480B (zh) 測試記憶體電路的方法以及記憶體電路
US11735265B2 (en) Nonvolatile semiconductor memory device and operating method thereof
US9754669B2 (en) Flash memory arrangement with a common read-write circuit shared by partial matrices of a memory column
US7076703B1 (en) Method and system for defining a redundancy window around a particular column in a memory array
US7095662B2 (en) Semiconductor memory device having first and second memory cell arrays and a program method thereof
US9003105B2 (en) Semiconductor memory device and method for writing therein
US20250336450A1 (en) Memory device and method of operating the memory device
US8804420B2 (en) Semiconductor memory device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200228

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20200228

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20200703

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200721

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20200819

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200918

R150 Certificate of patent or registration of utility model

Ref document number: 6768173

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250