ITRM20010516A1 - Architettura a schiera di memorie flash. - Google Patents

Architettura a schiera di memorie flash.

Info

Publication number
ITRM20010516A1
ITRM20010516A1 IT2001RM000516A ITRM20010516A ITRM20010516A1 IT RM20010516 A1 ITRM20010516 A1 IT RM20010516A1 IT 2001RM000516 A IT2001RM000516 A IT 2001RM000516A IT RM20010516 A ITRM20010516 A IT RM20010516A IT RM20010516 A1 ITRM20010516 A1 IT RM20010516A1
Authority
IT
Italy
Prior art keywords
flash memory
memory architecture
architecture
flash
memory
Prior art date
Application number
IT2001RM000516A
Other languages
English (en)
Inventor
Girolamo Gallo
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to IT2001RM000516A priority Critical patent/ITRM20010516A1/it
Publication of ITRM20010516A0 publication Critical patent/ITRM20010516A0/it
Priority to US10/228,824 priority patent/US6751121B2/en
Publication of ITRM20010516A1 publication Critical patent/ITRM20010516A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
IT2001RM000516A 2001-08-29 2001-08-29 Architettura a schiera di memorie flash. ITRM20010516A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2001RM000516A ITRM20010516A1 (it) 2001-08-29 2001-08-29 Architettura a schiera di memorie flash.
US10/228,824 US6751121B2 (en) 2001-08-29 2002-08-27 Flash memory array architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001RM000516A ITRM20010516A1 (it) 2001-08-29 2001-08-29 Architettura a schiera di memorie flash.

Publications (2)

Publication Number Publication Date
ITRM20010516A0 ITRM20010516A0 (it) 2001-08-29
ITRM20010516A1 true ITRM20010516A1 (it) 2003-02-28

Family

ID=11455749

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001RM000516A ITRM20010516A1 (it) 2001-08-29 2001-08-29 Architettura a schiera di memorie flash.

Country Status (2)

Country Link
US (1) US6751121B2 (it)
IT (1) ITRM20010516A1 (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
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US7577207B2 (en) * 2002-07-03 2009-08-18 Dtvg Licensing, Inc. Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
US6975538B2 (en) * 2003-10-08 2005-12-13 Micron Technology, Inc. Memory block erasing in a flash memory device
US7263027B2 (en) * 2004-10-14 2007-08-28 Broadcom Corporation Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features
KR100648281B1 (ko) * 2005-01-14 2006-11-23 삼성전자주식회사 보안 리던던시 블록을 구비한 낸드 플래시 메모리 장치
US7268023B2 (en) * 2005-05-05 2007-09-11 Micron Technology, Inc. Method of forming a pseudo SOI substrate and semiconductor devices
US7289363B2 (en) * 2005-05-19 2007-10-30 Micron Technology, Inc. Memory cell repair using fuse programming method in a flash memory device
US7551498B2 (en) * 2006-12-15 2009-06-23 Atmel Corporation Implementation of column redundancy for a flash memory with a high write parallelism
US7539062B2 (en) * 2006-12-20 2009-05-26 Micron Technology, Inc. Interleaved memory program and verify method, device and system
US8144517B2 (en) * 2008-02-22 2012-03-27 Samsung Electronics Co., Ltd. Multilayered nonvolatile memory with adaptive control
JP2013254538A (ja) * 2012-06-06 2013-12-19 Toshiba Corp 不揮発性半導体記憶装置
KR101997623B1 (ko) 2013-02-26 2019-07-09 삼성전자주식회사 메모리 장치 및 그것을 포함하는 메모리 시스템
US8971137B2 (en) * 2013-03-07 2015-03-03 Intel Corporation Bit based fuse repair
CN107808683B (zh) * 2016-09-09 2021-02-19 硅存储技术公司 用于读取阵列中的闪存单元的带位线预充电电路的改进读出放大器
US10269444B2 (en) * 2016-12-21 2019-04-23 Sandisk Technologies Llc Memory with bit line short circuit detection and masking of groups of bad bit lines
US10141065B1 (en) 2017-08-29 2018-11-27 Cypress Semiconductor Corporation Row redundancy with distributed sectors
US10838726B1 (en) 2019-11-05 2020-11-17 Sandisk Technologies Llc Asynchronous FIFO buffer for redundant columns in memory device
US11354209B2 (en) * 2020-04-13 2022-06-07 Sandisk Technologies Llc Column redundancy data architecture for yield improvement

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12045A (en) * 1854-12-05 Franklin darracott
US58689A (en) * 1866-10-09 Improvement in horse-rakes
US31052A (en) * 1861-01-01 Improved watchman s time-detector
US5150330A (en) * 1990-01-24 1992-09-22 Vlsi Technology, Inc. Interblock dispersed-word memory architecture
US5241496A (en) * 1991-08-19 1993-08-31 Micron Technology, Inc. Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells
US6230233B1 (en) * 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US5892703A (en) * 1997-06-13 1999-04-06 Micron Technology, Inc, Memory architecture and decoder addressing
US6005813A (en) * 1997-11-12 1999-12-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6141286A (en) * 1998-08-21 2000-10-31 Micron Technology, Inc. Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines
US6310805B1 (en) * 2000-03-07 2001-10-30 Advanced Micro Devices, Inc. Architecture for a dual-bank page mode memory with redundancy
US6356474B1 (en) * 2000-12-07 2002-03-12 Micron Technology, Inc. Efficient open-array memory device architecture and method
US6731527B2 (en) 2001-07-11 2004-05-04 Micron Technology, Inc. Architecture for a semiconductor memory device for minimizing interference and cross-coupling between control signal lines and power lines
US6625081B2 (en) 2001-08-13 2003-09-23 Micron Technology, Inc. Synchronous flash memory with virtual segment architecture
ITRM20010524A1 (it) 2001-08-30 2003-02-28 Micron Technology Inc Struttura a schiera di memoria flash.
US6587383B1 (en) * 2002-03-19 2003-07-01 Micron Technology, Inc. Erase block architecture for non-volatile memory

Also Published As

Publication number Publication date
US6751121B2 (en) 2004-06-15
US20030053348A1 (en) 2003-03-20
ITRM20010516A0 (it) 2001-08-29

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