JP6757737B2 - 容量性構造のための導電性スルーポリマービア - Google Patents
容量性構造のための導電性スルーポリマービア Download PDFInfo
- Publication number
- JP6757737B2 JP6757737B2 JP2017550144A JP2017550144A JP6757737B2 JP 6757737 B2 JP6757737 B2 JP 6757737B2 JP 2017550144 A JP2017550144 A JP 2017550144A JP 2017550144 A JP2017550144 A JP 2017550144A JP 6757737 B2 JP6757737 B2 JP 6757737B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic system
- capacitor
- polymer
- conductive
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/06—Planarisation of inorganic insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/43—Layouts of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/495—Capacitive arrangements or effects of, or between wiring layers
- H10W20/496—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0215—Metallic fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Ceramic Capacitors (AREA)
- Dc-Dc Converters (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/668,085 US9572261B2 (en) | 2015-03-25 | 2015-03-25 | Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips |
| US14/668,085 | 2015-03-25 | ||
| PCT/US2016/023817 WO2016154339A1 (en) | 2015-03-25 | 2016-03-23 | Conductive through-polymer vias for capacitive structures |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018515909A JP2018515909A (ja) | 2018-06-14 |
| JP2018515909A5 JP2018515909A5 (https=) | 2019-04-04 |
| JP6757737B2 true JP6757737B2 (ja) | 2020-09-23 |
Family
ID=56976000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017550144A Active JP6757737B2 (ja) | 2015-03-25 | 2016-03-23 | 容量性構造のための導電性スルーポリマービア |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US9572261B2 (https=) |
| JP (1) | JP6757737B2 (https=) |
| CN (1) | CN107251255B (https=) |
| WO (1) | WO2016154339A1 (https=) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9572261B2 (en) * | 2015-03-25 | 2017-02-14 | Texas Instruments Incorporated | Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips |
| TWI653715B (zh) * | 2016-05-13 | 2019-03-11 | Murata Manufacturing Co., Ltd. | 晶圓級封裝及電容器 |
| US9865527B1 (en) | 2016-12-22 | 2018-01-09 | Texas Instruments Incorporated | Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance and insulation |
| US9941194B1 (en) | 2017-02-21 | 2018-04-10 | Texas Instruments Incorporated | Packaged semiconductor device having patterned conductance dual-material nanoparticle adhesion layer |
| US20190051596A1 (en) * | 2017-08-10 | 2019-02-14 | Applied Materials, Inc. | Method of increasing embedded 3d metal-insulator-metal (mim) capacitor capacitance density for wafer level packaging |
| US10867752B2 (en) | 2017-09-28 | 2020-12-15 | Samsung Electro-Mechanics Co., Ltd. | Capacitor and method of manufacturing the same |
| US10566276B2 (en) | 2017-11-08 | 2020-02-18 | Texas Instruments Incorporated | Packaged semiconductor system having unidirectional connections to discrete components |
| KR102785407B1 (ko) | 2019-03-12 | 2025-03-21 | 교세라 에이브이엑스 컴포넌츠 코포레이션 | 고전력, 양면 박막 필터 |
| CN115039190B (zh) * | 2020-03-24 | 2023-08-25 | 株式会社村田制作所 | 电容器 |
| DE102020119611A1 (de) | 2020-07-24 | 2022-01-27 | Infineon Technologies Ag | Schaltungsanordnung und verfahren zum bilden einer schaltungsanordnung |
| US11315453B1 (en) * | 2020-11-08 | 2022-04-26 | Innolux Corporation | Tiled display device with a test circuit |
| CN119732205A (zh) * | 2022-07-29 | 2025-03-28 | 索尼半导体解决方案公司 | 半导体装置及其制造方法、电子装置 |
| KR20240104602A (ko) * | 2022-12-28 | 2024-07-05 | 삼성전기주식회사 | 복합 전자 부품 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08116030A (ja) * | 1994-10-12 | 1996-05-07 | Inter Nix Kk | 半導体集積回路装置 |
| EP0837504A3 (en) | 1996-08-20 | 1999-01-07 | Ramtron International Corporation | Partially or completely encapsulated ferroelectric device |
| US5825628A (en) | 1996-10-03 | 1998-10-20 | International Business Machines Corporation | Electronic package with enhanced pad design |
| JP2002057037A (ja) * | 2000-08-09 | 2002-02-22 | Fuji Electric Co Ltd | 複合集積回路およびその製造方法 |
| JP4795521B2 (ja) * | 2000-10-16 | 2011-10-19 | 富士通株式会社 | 半導体装置及びその製造方法 |
| US6388207B1 (en) | 2000-12-29 | 2002-05-14 | Intel Corporation | Electronic assembly with trench structures and methods of manufacture |
| US8174017B2 (en) | 2005-08-17 | 2012-05-08 | Georgia Tech Research Corporation | Integrating three-dimensional high capacitance density structures |
| JP2008071935A (ja) * | 2006-09-14 | 2008-03-27 | Toshiba Corp | 半導体装置 |
| DE102006055576A1 (de) * | 2006-11-21 | 2008-05-29 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Herstellen eines dehnbaren Schaltungsträgers und dehnbarer Schaltungsträger |
| JP4869991B2 (ja) * | 2007-03-14 | 2012-02-08 | 富士通株式会社 | キャパシタ内蔵ウェハレベルパッケージ及びその製造方法 |
| CN101682252B (zh) | 2007-05-10 | 2013-10-23 | Nxp股份有限公司 | 包含可重构电容器单元的直流-直流变换器 |
| JP4962339B2 (ja) | 2008-02-07 | 2012-06-27 | 富士通株式会社 | キャパシタの製造方法 |
| US8084841B2 (en) | 2009-05-05 | 2011-12-27 | Georgia Tech Research | Systems and methods for providing high-density capacitors |
| JP2011040602A (ja) * | 2009-08-12 | 2011-02-24 | Renesas Electronics Corp | 電子装置およびその製造方法 |
| CN102906835B (zh) * | 2009-12-16 | 2016-08-17 | 艾普瑞特材料技术有限责任公司 | 具有三维高比表面积电极的电容器和制造方法 |
| JP2011159856A (ja) * | 2010-02-02 | 2011-08-18 | Sanyo Electric Co Ltd | コンデンサ用電極体、コンデンサおよびそれらの製造方法 |
| JP2011192783A (ja) * | 2010-03-15 | 2011-09-29 | Nissin Electric Co Ltd | コンデンサ装置 |
| JP2013207197A (ja) * | 2012-03-29 | 2013-10-07 | Denso Corp | 多層基板の製造方法 |
| US9572261B2 (en) * | 2015-03-25 | 2017-02-14 | Texas Instruments Incorporated | Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips |
-
2015
- 2015-03-25 US US14/668,085 patent/US9572261B2/en active Active
-
2016
- 2016-03-23 JP JP2017550144A patent/JP6757737B2/ja active Active
- 2016-03-23 WO PCT/US2016/023817 patent/WO2016154339A1/en not_active Ceased
- 2016-03-23 CN CN201680012146.5A patent/CN107251255B/zh active Active
- 2016-10-31 US US15/339,550 patent/US9852979B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9572261B2 (en) | 2017-02-14 |
| US9852979B2 (en) | 2017-12-26 |
| JP2018515909A (ja) | 2018-06-14 |
| WO2016154339A1 (en) | 2016-09-29 |
| US20160286654A1 (en) | 2016-09-29 |
| CN107251255B (zh) | 2020-06-26 |
| US20170047283A1 (en) | 2017-02-16 |
| CN107251255A (zh) | 2017-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6757737B2 (ja) | 容量性構造のための導電性スルーポリマービア | |
| US11177204B2 (en) | Power electronics package and method of manufacturing thereof | |
| US10211177B2 (en) | High power semiconductor package subsystems | |
| TWI467674B (zh) | 微電子封裝組件及其製造方法 | |
| US8524532B1 (en) | Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein | |
| TWI455214B (zh) | 用於資料處理系統之整合模組 | |
| JP7277056B2 (ja) | 一体化された電磁干渉シールドを備えるエレクトロニクスパッケージおよびその製造方法 | |
| CN104008980B (zh) | 用于制作半导体器件的方法 | |
| US10756013B2 (en) | Packaged semiconductor system having unidirectional connections to discrete components | |
| CN119361547A (zh) | 一种高频大功率封装模组及混合基板 | |
| TW202131461A (zh) | 半導體結構 | |
| JP2018515909A5 (https=) | ||
| CN107086212A (zh) | 具有集成无源部件的引线框架上的半导体器件 | |
| CN100524717C (zh) | 芯片内埋的模块化结构 | |
| US20180247924A1 (en) | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof | |
| WO2012116157A2 (en) | Chip module embedded in pcb substrate | |
| CN112530907B (zh) | 一种无源器件堆叠的多芯片封装结构和方法 | |
| US12207399B2 (en) | Component carrier having a double dielectric layer and method of manufacturing the same | |
| KR101341619B1 (ko) | 반도체 패키지 및 그의 제조 방법 | |
| US10104764B2 (en) | Electronic device package with vertically integrated capacitors | |
| US20140239466A1 (en) | Electronic Device | |
| US20250372509A1 (en) | Microelectronic device package with hybrid isolation laminate | |
| EP3352212B1 (en) | Power electronics package and method of manufacturing thereof | |
| CN117059616A (zh) | 热耦接至无源元件的半导体器件封装 | |
| KR20180092379A (ko) | 전력 전자 패키지 및 그 제조 방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20170925 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190221 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190221 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200423 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200520 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200520 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200805 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200831 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6757737 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |