JP6722745B2 - チップホルダ付きリードフレーム構造 - Google Patents

チップホルダ付きリードフレーム構造 Download PDF

Info

Publication number
JP6722745B2
JP6722745B2 JP2018215661A JP2018215661A JP6722745B2 JP 6722745 B2 JP6722745 B2 JP 6722745B2 JP 2018215661 A JP2018215661 A JP 2018215661A JP 2018215661 A JP2018215661 A JP 2018215661A JP 6722745 B2 JP6722745 B2 JP 6722745B2
Authority
JP
Japan
Prior art keywords
chip holder
lead frame
portions
wiring
frame structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018215661A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019186522A (ja
Inventor
振豊 朱
振豊 朱
原富 陳
原富 陳
Original Assignee
復盛精密工業股▲ふん▼有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 復盛精密工業股▲ふん▼有限公司 filed Critical 復盛精密工業股▲ふん▼有限公司
Publication of JP2019186522A publication Critical patent/JP2019186522A/ja
Application granted granted Critical
Publication of JP6722745B2 publication Critical patent/JP6722745B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)
JP2018215661A 2018-04-16 2018-11-16 チップホルダ付きリードフレーム構造 Active JP6722745B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107112938 2018-04-16
TW107112938A TWI653724B (zh) 2018-04-16 2018-04-16 具有晶片座的導線架結構

Publications (2)

Publication Number Publication Date
JP2019186522A JP2019186522A (ja) 2019-10-24
JP6722745B2 true JP6722745B2 (ja) 2020-07-15

Family

ID=66590627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018215661A Active JP6722745B2 (ja) 2018-04-16 2018-11-16 チップホルダ付きリードフレーム構造

Country Status (3)

Country Link
JP (1) JP6722745B2 (zh)
CN (1) CN110391204A (zh)
TW (1) TWI653724B (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316269A (ja) * 1995-05-16 1996-11-29 Fujitsu Ltd 半導体チップおよびチップホルダとそれに用いた半導体装置の製造方法
US20100164078A1 (en) * 2008-12-31 2010-07-01 Ruben Madrid Package assembly for semiconductor devices
TWI490988B (zh) * 2012-03-21 2015-07-01 Chipmos Technologies Inc 半導體封裝結構
TWM552187U (zh) * 2017-05-18 2017-11-21 Fusheng Electronics Corp 具線路之導線架結構
TWM567481U (zh) * 2018-04-16 2018-09-21 復盛精密工業股份有限公司 具有晶片座的導線架結構

Also Published As

Publication number Publication date
TW201944563A (zh) 2019-11-16
CN110391204A (zh) 2019-10-29
JP2019186522A (ja) 2019-10-24
TWI653724B (zh) 2019-03-11

Similar Documents

Publication Publication Date Title
US7679172B2 (en) Semiconductor package without chip carrier and fabrication method thereof
JP3526788B2 (ja) 半導体装置の製造方法
JP5349755B2 (ja) 表面実装の発光チップパッケージ
US8659146B2 (en) Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
JP5802695B2 (ja) 半導体装置、半導体装置の製造方法
JP3483720B2 (ja) 半導体装置
KR20090093162A (ko) 전력 소자 패키지 및 그 제조 방법
KR20090050752A (ko) 반도체 패키지 및 그의 제조방법
JP2002033011A (ja) 発光装置
JP5169964B2 (ja) モールドパッケージの実装構造および実装方法
KR100575216B1 (ko) 발광소자용 패캐지 베이스
JP7088224B2 (ja) 半導体モジュールおよびこれに用いられる半導体装置
JPH0883865A (ja) 樹脂封止型半導体装置
JP6722745B2 (ja) チップホルダ付きリードフレーム構造
JP5912471B2 (ja) 半導体デバイス
JPH08236665A (ja) 樹脂封止型半導体装置及びその製造方法
TWM567481U (zh) 具有晶片座的導線架結構
JP5066971B2 (ja) モールドパッケージの実装構造
JP2660732B2 (ja) 半導体装置
JPH11265964A (ja) 半導体装置とその製造方法
JPH06132441A (ja) 樹脂封止型半導体装置及びその製造方法
JP3314574B2 (ja) 半導体装置の製造方法
JP2612468B2 (ja) 電子部品搭載用基板
US20220392863A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
JPH0878461A (ja) 放熱板付き半導体装置及びその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181116

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200204

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200422

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200526

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200622

R150 Certificate of patent or registration of utility model

Ref document number: 6722745

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250