JP6695166B2 - リードフレーム、及び半導体パッケージの製造方法 - Google Patents

リードフレーム、及び半導体パッケージの製造方法 Download PDF

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Publication number
JP6695166B2
JP6695166B2 JP2016032421A JP2016032421A JP6695166B2 JP 6695166 B2 JP6695166 B2 JP 6695166B2 JP 2016032421 A JP2016032421 A JP 2016032421A JP 2016032421 A JP2016032421 A JP 2016032421A JP 6695166 B2 JP6695166 B2 JP 6695166B2
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Japan
Prior art keywords
lead frame
end portion
base end
sealing resin
resin
Prior art date
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Active
Application number
JP2016032421A
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English (en)
Japanese (ja)
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JP2017152496A (ja
Inventor
石橋　貴弘
貴弘 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tech Inc
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Mitsui High Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tech Inc filed Critical Mitsui High Tech Inc
Priority to JP2016032421A priority Critical patent/JP6695166B2/ja
Priority to CN201710078265.7A priority patent/CN107104089B/zh
Priority to TW106105459A priority patent/TW201801261A/zh
Publication of JP2017152496A publication Critical patent/JP2017152496A/ja
Application granted granted Critical
Publication of JP6695166B2 publication Critical patent/JP6695166B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2016032421A 2016-02-23 2016-02-23 リードフレーム、及び半導体パッケージの製造方法 Active JP6695166B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2016032421A JP6695166B2 (ja) 2016-02-23 2016-02-23 リードフレーム、及び半導体パッケージの製造方法
CN201710078265.7A CN107104089B (zh) 2016-02-23 2017-02-14 引线框、以及半导体封装的制造方法
TW106105459A TW201801261A (zh) 2016-02-23 2017-02-18 導線架、及半導體封裝之製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016032421A JP6695166B2 (ja) 2016-02-23 2016-02-23 リードフレーム、及び半導体パッケージの製造方法

Publications (2)

Publication Number Publication Date
JP2017152496A JP2017152496A (ja) 2017-08-31
JP6695166B2 true JP6695166B2 (ja) 2020-05-20

Family

ID=59676457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016032421A Active JP6695166B2 (ja) 2016-02-23 2016-02-23 リードフレーム、及び半導体パッケージの製造方法

Country Status (3)

Country Link
JP (1) JP6695166B2 (zh)
CN (1) CN107104089B (zh)
TW (1) TW201801261A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118103973A (zh) * 2021-10-13 2024-05-28 罗姆股份有限公司 半导体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
JP4417541B2 (ja) * 2000-10-23 2010-02-17 ローム株式会社 半導体装置およびその製造方法
KR20020093250A (ko) * 2001-06-07 2002-12-16 삼성전자 주식회사 리드 노출형 리드 프레임 및 그를 이용한 리드 노출형반도체 패키지
JP2009302209A (ja) * 2008-06-11 2009-12-24 Nec Electronics Corp リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法

Also Published As

Publication number Publication date
CN107104089B (zh) 2019-11-22
TW201801261A (zh) 2018-01-01
CN107104089A (zh) 2017-08-29
JP2017152496A (ja) 2017-08-31

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