JP6612189B2 - 配線基板、半導体装置、および、配線基板の製造方法 - Google Patents

配線基板、半導体装置、および、配線基板の製造方法 Download PDF

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Publication number
JP6612189B2
JP6612189B2 JP2016125670A JP2016125670A JP6612189B2 JP 6612189 B2 JP6612189 B2 JP 6612189B2 JP 2016125670 A JP2016125670 A JP 2016125670A JP 2016125670 A JP2016125670 A JP 2016125670A JP 6612189 B2 JP6612189 B2 JP 6612189B2
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JP
Japan
Prior art keywords
layer
resin
wiring
wiring layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016125670A
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English (en)
Japanese (ja)
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JP2017228734A5 (enExample
JP2017228734A (ja
Inventor
晃輔 塚本
規良 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2016125670A priority Critical patent/JP6612189B2/ja
Priority to US15/624,080 priority patent/US10074601B2/en
Publication of JP2017228734A publication Critical patent/JP2017228734A/ja
Publication of JP2017228734A5 publication Critical patent/JP2017228734A5/ja
Application granted granted Critical
Publication of JP6612189B2 publication Critical patent/JP6612189B2/ja
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Classifications

    • H10W70/685—
    • H10W70/05—
    • H10W70/095—
    • H10W70/635—
    • H10W70/65—
    • H10W90/701—
    • H10W99/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H10W70/695—
    • H10W74/15—
    • H10W90/724—
    • H10W90/734—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Geometry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2016125670A 2016-06-24 2016-06-24 配線基板、半導体装置、および、配線基板の製造方法 Active JP6612189B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016125670A JP6612189B2 (ja) 2016-06-24 2016-06-24 配線基板、半導体装置、および、配線基板の製造方法
US15/624,080 US10074601B2 (en) 2016-06-24 2017-06-15 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016125670A JP6612189B2 (ja) 2016-06-24 2016-06-24 配線基板、半導体装置、および、配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2017228734A JP2017228734A (ja) 2017-12-28
JP2017228734A5 JP2017228734A5 (enExample) 2019-02-14
JP6612189B2 true JP6612189B2 (ja) 2019-11-27

Family

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Family Applications (1)

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JP2016125670A Active JP6612189B2 (ja) 2016-06-24 2016-06-24 配線基板、半導体装置、および、配線基板の製造方法

Country Status (2)

Country Link
US (1) US10074601B2 (enExample)
JP (1) JP6612189B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
US10785871B1 (en) * 2018-12-12 2020-09-22 Vlt, Inc. Panel molded electronic assemblies with integral terminals
US10879157B2 (en) * 2018-11-16 2020-12-29 Xilinx, Inc. High density substrate and stacked silicon package assembly having the same
JP7509395B2 (ja) * 2019-10-30 2024-07-02 株式会社ライジングテクノロジーズ 配線基板
TWI757996B (zh) 2020-08-24 2022-03-11 錼創顯示科技股份有限公司 微型發光二極體顯示矩陣模組
US20230420353A1 (en) * 2022-06-23 2023-12-28 Intel Corporation Asymmetrical dielectric-to-metal adhesion architecture for electronic packages
JP2024086199A (ja) * 2022-12-16 2024-06-27 イビデン株式会社 配線基板およびその製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5916453A (en) * 1996-09-20 1999-06-29 Fujitsu Limited Methods of planarizing structures on wafers and substrates by polishing
JPH10322024A (ja) * 1997-05-16 1998-12-04 Hitachi Ltd 非貫通ビアホールを有するビルドアップ多層プリント配線板及びその製造方法
JP3976954B2 (ja) * 1999-08-27 2007-09-19 新光電気工業株式会社 多層配線基板の製造方法及び半導体装置
US7565738B2 (en) * 2004-05-31 2009-07-28 Sanyo Electric Co., Ltd. Method for manufacturing circuit device
JP2006019361A (ja) * 2004-06-30 2006-01-19 Sanyo Electric Co Ltd 回路装置およびその製造方法
KR100613375B1 (ko) * 2004-08-13 2006-08-17 동부일렉트로닉스 주식회사 반도체 소자의 구리 배선 및 그 형성 방법
US20070281464A1 (en) * 2006-06-01 2007-12-06 Shih-Ping Hsu Multi-layer circuit board with fine pitches and fabricating method thereof
JPWO2013161527A1 (ja) * 2012-04-26 2015-12-24 日本特殊陶業株式会社 多層配線基板及びその製造方法
US9000302B2 (en) * 2013-04-17 2015-04-07 Shinko Electric Industries Co., Ltd. Wiring board
JP6169955B2 (ja) 2013-04-17 2017-07-26 新光電気工業株式会社 配線基板及びその製造方法
JP6133227B2 (ja) * 2014-03-27 2017-05-24 新光電気工業株式会社 配線基板及びその製造方法
JP2015222753A (ja) * 2014-05-22 2015-12-10 イビデン株式会社 プリント配線板及びその製造方法

Also Published As

Publication number Publication date
US10074601B2 (en) 2018-09-11
JP2017228734A (ja) 2017-12-28
US20170372991A1 (en) 2017-12-28

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