JP6600573B2 - 配線基板及び半導体パッケージ - Google Patents

配線基板及び半導体パッケージ Download PDF

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Publication number
JP6600573B2
JP6600573B2 JP2016014736A JP2016014736A JP6600573B2 JP 6600573 B2 JP6600573 B2 JP 6600573B2 JP 2016014736 A JP2016014736 A JP 2016014736A JP 2016014736 A JP2016014736 A JP 2016014736A JP 6600573 B2 JP6600573 B2 JP 6600573B2
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Japan
Prior art keywords
wiring
layer
substrate
insulating layer
pattern
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JP2016014736A
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Japanese (ja)
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JP2016195238A5 (https=
JP2016195238A (ja
Inventor
亮 深澤
純廣 市川
道夫 堀内
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to US15/083,926 priority Critical patent/US9960120B2/en
Publication of JP2016195238A publication Critical patent/JP2016195238A/ja
Publication of JP2016195238A5 publication Critical patent/JP2016195238A5/ja
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  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2016014736A 2015-03-31 2016-01-28 配線基板及び半導体パッケージ Active JP6600573B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/083,926 US9960120B2 (en) 2015-03-31 2016-03-29 Wiring substrate with buried substrate having linear conductors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015070694 2015-03-31
JP2015070694 2015-03-31

Publications (3)

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JP2016195238A JP2016195238A (ja) 2016-11-17
JP2016195238A5 JP2016195238A5 (https=) 2019-01-10
JP6600573B2 true JP6600573B2 (ja) 2019-10-30

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JP2016014736A Active JP6600573B2 (ja) 2015-03-31 2016-01-28 配線基板及び半導体パッケージ

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7278114B2 (ja) * 2019-03-13 2023-05-19 イビデン株式会社 プリント配線板の製造方法
JP2021027168A (ja) * 2019-08-05 2021-02-22 イビデン株式会社 配線基板及びその製造方法
JP2021040021A (ja) * 2019-09-03 2021-03-11 富士通インターコネクトテクノロジーズ株式会社 基板、基板の製造方法、及び電子機器
CN113013125B (zh) * 2019-12-20 2024-07-09 奥特斯奥地利科技与系统技术有限公司 嵌入有在侧向上位于堆叠体的导电结构之间的内插件的部件承载件
KR102628149B1 (ko) * 2020-11-27 2024-01-24 주식회사 심텍 브릿지 패턴을 구비하는 인쇄회로기판 및 이의 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4726546B2 (ja) * 2005-06-03 2011-07-20 日本特殊陶業株式会社 配線基板の製造方法
JP2008060208A (ja) * 2006-08-30 2008-03-13 Kyocera Corp 多層配線基板およびそれを用いたプローブカード
JPWO2010134511A1 (ja) * 2009-05-20 2012-11-12 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP5436963B2 (ja) * 2009-07-21 2014-03-05 新光電気工業株式会社 配線基板及び半導体装置
JP5363384B2 (ja) * 2010-03-11 2013-12-11 新光電気工業株式会社 配線基板及びその製造方法
JP5001395B2 (ja) * 2010-03-31 2012-08-15 イビデン株式会社 配線板及び配線板の製造方法
JP5598212B2 (ja) * 2010-09-29 2014-10-01 パナソニック株式会社 ハイブリッドコア基板とその製造方法、半導体集積回路パッケージ、及びビルドアップ基板とその製造方法
JP5775747B2 (ja) * 2011-06-03 2015-09-09 新光電気工業株式会社 配線基板及びその製造方法
JP2013004576A (ja) * 2011-06-13 2013-01-07 Shinko Electric Ind Co Ltd 半導体装置
JP5827166B2 (ja) * 2012-04-09 2015-12-02 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP6105209B2 (ja) * 2012-04-25 2017-03-29 京セラ株式会社 配線基板およびこれを用いた実装構造体
CN103843471A (zh) * 2012-04-26 2014-06-04 日本特殊陶业株式会社 多层布线基板及其制造方法
JP2014165218A (ja) * 2013-02-21 2014-09-08 Ibiden Co Ltd 配線板、及び、配線板の製造方法

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JP2016195238A (ja) 2016-11-17

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