JP6594246B2 - 表示装置 - Google Patents
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- JP6594246B2 JP6594246B2 JP2016073037A JP2016073037A JP6594246B2 JP 6594246 B2 JP6594246 B2 JP 6594246B2 JP 2016073037 A JP2016073037 A JP 2016073037A JP 2016073037 A JP2016073037 A JP 2016073037A JP 6594246 B2 JP6594246 B2 JP 6594246B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1712—Layout
- H01L2224/17179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1751—Function
- H01L2224/17515—Bump connectors having different functions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1426—Driver
Description
図1は、本実施形態に係る表示装置の一例を表す説明図である。図2は、表示部の一例を示す断面図である。図3は、図1の表示装置を表すブロック図である。図4は、画素回路の一例を示す回路図である。図1は模式的に表したものであり、実際の寸法、形状と同一とは限らない。
図10は、第2実施形態におけるドライバICの端子が載置される基板の接続電極及び配線を拡大して示す模式図である。図11は、図10のXI−XI断面の模式図である。なお、上述した第1実施形態で説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。
図12は、第2実施形態の第1変形例におけるドライバICの端子が載置される基板の接続電極及び配線を拡大して示す模式図である。なお、上述した第1実施形態及び第2実施形態で説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。
図13は、第2実施形態の第2変形例におけるドライバICの端子が載置される基板の接続電極及び配線を拡大して示す模式図である。なお、上述した第1実施形態、第2実施形態及び第2実施形態の第1変形例で説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。
図14は、第3実施形態におけるドライバICの端子が載置される基板の接続電極及び配線を拡大して示す模式図である。なお、上述した第1実施形態、第2実施形態及び第2実施形態の各変形例のいずれかで説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。
図15は、第3実施形態の第1変形例におけるドライバICの端子が載置される基板の接続電極及び配線を拡大して示す模式図である。なお、上述した第1実施形態、第2実施形態及び第2実施形態の各変形例のいずれかで説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。
図16は、第3実施形態の評価例について説明する説明図である。なお、上述した第3実施形態で説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。
2 表示部
6 バックライト
21 表示領域
21a 第1辺
21b 第2辺
22 走査線駆動回路
23 走査線駆動回路
24 走査線
25 信号線
31、32、34、35 接続端子
39 内部配線
41 第1バンプ
43A、43B、43C、43D 検査用配線
48 第2バンプ
46A、46B、46C、46D 検査用バンプ
29b 額縁領域
60 画素基板
200 配線
Claims (8)
- 表示領域と、表示領域の周囲にある非表示領域とを備える基板と、
複数の接続端子を備え、かつ前記非表示領域に向けて固定される第1面を有する、少なくとも1つのドライバICと、
前記表示領域へ信号を供給する第1配線と、
前記第1配線と電気的にそれぞれ接続され、前記ドライバICの長手方向に並ぶ複数の第1バンプと、
外部へ入出力するための第2配線と、
前記第2配線と電気的にそれぞれ接続される複数の第2バンプと、
複数の検査用配線と、
複数の前記検査用配線のそれぞれが接続される複数の検査用バンプと、を備え、
前記ドライバICの接続端子は、前記第1バンプ又は前記第2バンプと平面視で重なり合う複数の第1接続端子と、前記第1バンプ又は前記第2バンプと平面視で重なり合わない位置であって、かつ平面視で前記第1バンプの前記長手方向に並ぶ位置に配置され、前記第1配線に接続されない第2接続端子と、を含み、
少なくとも1つの前記検査用配線が、少なくとも1つの前記第2接続端子との間に、接続用導電体を有しており、平面視で前記検査用配線が前記ドライバICの外側に引き出されて、一端が前記検査用バンプに接続され、他端が前記第2接続端子に前記接続用導電体を介して電気的に接続され、
前記検査用配線において、平面視で前記検査用配線の基本幅より一部の幅が狭くなる第1幅狭部が前記検査用バンプと、前記第2接続端子に接続する前記接続用導電体がある位置との間に少なくとも1つある、表示装置。 - 平面視で前記第1バンプに重なり合う前記複数の第1接続端子は、平面視で前記ドライバICの長手方向の列が複数列となるように並んでおり、
前記検査用配線が平面視で重なり合う前記第2接続端子は、前記ドライバICの短手方向の内側にあり、かつ平面視で前記第1バンプに重なり合う第1接続端子の列に並んで配置されている、請求項1に記載の表示装置。 - 平面視で前記ドライバICの長手方向にみて、前記第2接続端子、複数の第1接続端子、前記第2接続端子の順に並んでいる、請求項1又は2に記載の表示装置。
- 平面視で前記ドライバICの長手方向にみて、複数の前記第2接続端子、複数の第1接続端子、複数の前記第2接続端子の順に並んでいる、請求項1又は2に記載の表示装置。
- 平面視で前記ドライバICの長手方向にみて、前記第2接続端子が、前記第1接続端子よりも、前記ドライバICの短手辺に近い、請求項1から4のいずれか1項に記載の表示装置。
- 平面視で4つの前記検査用配線が1つの前記ドライバICの外側に引き出されており、前記第1幅狭部を有する検査用配線が前記第2バンプよりも前記第1バンプの近くまで延びている、請求項1から5のいずれか1項に記載の表示装置。
- 2つの前記検査用配線のそれぞれが隣り合う前記第2接続端子のそれぞれに平面視で重なり合うとともに、隣り合う前記第2接続端子が前記ドライバICの内部で短絡している、請求項1から6のいずれか1項に記載の表示装置。
- 2つの前記検査用配線の両方が1つの前記第2接続端子に平面視で重なり合う、請求項1から6のいずれか1項に記載の表示装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2016073037A JP6594246B2 (ja) | 2016-03-31 | 2016-03-31 | 表示装置 |
US15/469,664 US10529744B2 (en) | 2016-03-31 | 2017-03-27 | Display device |
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JP2016073037A JP6594246B2 (ja) | 2016-03-31 | 2016-03-31 | 表示装置 |
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JP2017181984A JP2017181984A (ja) | 2017-10-05 |
JP6594246B2 true JP6594246B2 (ja) | 2019-10-23 |
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JP (1) | JP6594246B2 (ja) |
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KR102628847B1 (ko) * | 2019-06-12 | 2024-01-25 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
TWI747303B (zh) * | 2020-05-29 | 2021-11-21 | 友達光電股份有限公司 | 測試電極組及測試系統 |
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JPS63102329A (ja) * | 1986-10-20 | 1988-05-07 | Seiko Epson Corp | 半導体集積回路素子実装方法 |
JPH0682802A (ja) * | 1992-08-31 | 1994-03-25 | Hitachi Ltd | 液晶表示装置 |
JPH0864750A (ja) * | 1994-08-23 | 1996-03-08 | Toshiba Corp | 半導体装置 |
JPH08110526A (ja) * | 1994-10-07 | 1996-04-30 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ基板の集合基板 |
US6033939A (en) * | 1998-04-21 | 2000-03-07 | International Business Machines Corporation | Method for providing electrically fusible links in copper interconnection |
JP3989631B2 (ja) * | 1998-08-31 | 2007-10-10 | セイコーインスツル株式会社 | 半導体装置 |
JP2004006705A (ja) * | 2002-04-08 | 2004-01-08 | Seiko Instruments Inc | 半導体装置の実装構造および回路基板 |
JP2004287032A (ja) * | 2003-03-20 | 2004-10-14 | Denso Corp | 薄膜表示素子及び、薄膜表示素子への電圧印加方法 |
JP2006309161A (ja) * | 2005-03-29 | 2006-11-09 | Sanyo Epson Imaging Devices Corp | 電気光学装置及び電子機器 |
JP4799952B2 (ja) | 2005-08-08 | 2011-10-26 | 三菱電機株式会社 | 液晶表示装置 |
JP2009047877A (ja) * | 2007-08-20 | 2009-03-05 | Epson Imaging Devices Corp | チップオングラス型表示モジュールおよびその実装検査方法 |
JP4992774B2 (ja) | 2008-03-14 | 2012-08-08 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
JP5239428B2 (ja) * | 2008-03-19 | 2013-07-17 | エプソンイメージングデバイス株式会社 | 電気光学装置及び電子機器 |
KR101491161B1 (ko) * | 2008-12-09 | 2015-02-06 | 엘지이노텍 주식회사 | 액정패널과 드라이버 ic 간의 접속상태를 테스트 하는 방법 및 이를 이용한 액정표시장치 |
US8183765B2 (en) | 2009-08-24 | 2012-05-22 | Global Oled Technology Llc | Controlling an electronic device using chiplets |
KR101783953B1 (ko) * | 2010-12-27 | 2017-10-11 | 삼성디스플레이 주식회사 | 표시 장치 및 그 검사 방법 |
KR102196093B1 (ko) * | 2014-02-04 | 2020-12-31 | 삼성디스플레이 주식회사 | 표시장치 |
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US10529744B2 (en) | 2020-01-07 |
JP2017181984A (ja) | 2017-10-05 |
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