JP6560965B2 - 分配されたキャパシティブ遅延追跡ブーストの支援回路 - Google Patents

分配されたキャパシティブ遅延追跡ブーストの支援回路 Download PDF

Info

Publication number
JP6560965B2
JP6560965B2 JP2015226232A JP2015226232A JP6560965B2 JP 6560965 B2 JP6560965 B2 JP 6560965B2 JP 2015226232 A JP2015226232 A JP 2015226232A JP 2015226232 A JP2015226232 A JP 2015226232A JP 6560965 B2 JP6560965 B2 JP 6560965B2
Authority
JP
Japan
Prior art keywords
voltage
boosting
boost
word line
distributed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015226232A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016100041A (ja
JP2016100041A5 (enExample
Inventor
バヤコウスキー マチェイ
バヤコウスキー マチェイ
フーバー ジャン−マイケル
フーバー ジャン−マイケル
ベンカテサ ラヴィ
ベンカテサ ラヴィ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2016100041A publication Critical patent/JP2016100041A/ja
Publication of JP2016100041A5 publication Critical patent/JP2016100041A5/ja
Application granted granted Critical
Publication of JP6560965B2 publication Critical patent/JP6560965B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/02Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP2015226232A 2014-11-20 2015-11-19 分配されたキャパシティブ遅延追跡ブーストの支援回路 Active JP6560965B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201462082611P 2014-11-20 2014-11-20
US62/082,611 2014-11-20
US14/813,103 US9502119B2 (en) 2014-11-20 2015-07-29 Distributed capacitive delay tracking boost-assist circuit
US14/813,103 2015-07-29

Publications (3)

Publication Number Publication Date
JP2016100041A JP2016100041A (ja) 2016-05-30
JP2016100041A5 JP2016100041A5 (enExample) 2018-10-11
JP6560965B2 true JP6560965B2 (ja) 2019-08-14

Family

ID=56010861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015226232A Active JP6560965B2 (ja) 2014-11-20 2015-11-19 分配されたキャパシティブ遅延追跡ブーストの支援回路

Country Status (4)

Country Link
US (1) US9502119B2 (enExample)
JP (1) JP6560965B2 (enExample)
KR (1) KR102427825B1 (enExample)
CN (1) CN105788621B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106898371B (zh) * 2017-02-24 2020-08-28 中国科学院上海微系统与信息技术研究所 三维存储器读出电路及其字线与位线电压配置方法
US11170830B2 (en) * 2020-02-11 2021-11-09 Taiwan Semiconductor Manufacturing Company Limited Word line driver for low voltage operation
CN115731964A (zh) * 2021-08-27 2023-03-03 长鑫存储技术有限公司 存储器和存储器的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2094086B (en) * 1981-03-03 1985-08-14 Tokyo Shibaura Electric Co Non-volatile semiconductor memory system
KR0137317B1 (ko) * 1994-12-29 1998-04-29 김광호 반도체 메모리소자의 활성싸이클에서 사용되는 승압회로
JPH10228773A (ja) * 1997-02-14 1998-08-25 Hitachi Ltd ダイナミック型ram
JP3412800B2 (ja) * 1997-05-27 2003-06-03 富士通株式会社 電圧発生回路を有した半導体装置
JP2001067868A (ja) * 1999-08-31 2001-03-16 Mitsubishi Electric Corp 半導体記憶装置
US7921388B2 (en) * 2006-09-18 2011-04-05 International Business Machines Corporation Wordline booster design structure and method of operating a wordine booster circuit
US8493812B2 (en) * 2010-10-28 2013-07-23 International Business Machines Corporation Boost circuit for generating an adjustable boost voltage
US8300446B2 (en) * 2010-12-13 2012-10-30 Texas Instruments Incorporated Ferroelectric random access memory with single plate line pulse during read
US8724373B2 (en) * 2011-09-12 2014-05-13 Qualcomm Incorporated Apparatus for selective word-line boost on a memory cell

Also Published As

Publication number Publication date
JP2016100041A (ja) 2016-05-30
US20160148659A1 (en) 2016-05-26
KR102427825B1 (ko) 2022-08-01
CN105788621A (zh) 2016-07-20
US9502119B2 (en) 2016-11-22
KR20160060557A (ko) 2016-05-30
CN105788621B (zh) 2019-08-20

Similar Documents

Publication Publication Date Title
US9503095B2 (en) Space-multiplexing DRAM-based reconfigurable logic
US9647453B2 (en) Dual supply memory
KR102546943B1 (ko) 8t 레지스터 파일들의 비경쟁 저전압 동작을 위한 분산된 글로벌-비트 라인 키퍼/프리차지/헤더 회로
JP6560965B2 (ja) 分配されたキャパシティブ遅延追跡ブーストの支援回路
TWI702485B (zh) 電子裝置及其驅動方法
CN111356966B (zh) 基于动态时钟和电压缩放定时对中央处理单元存储器分组以使用阵列功率复用器提高动态/泄漏功率
TWI826658B (zh) 時脈閘控系統
US10418975B2 (en) Low clock supply voltage interruptible sequential
KR102796749B1 (ko) 출력 리셋을 조정할 수 있는 집적 클럭 게이터 래치 구조
US20150109047A1 (en) Complementary metal-oxide-semiconductor (cmos) inverter circuit device
US9823688B2 (en) Level balanced clock tree
US20180034448A1 (en) System and method for providing an area efficient and design rule check (drc) friendly power sequencer for digital circuits
US11170845B1 (en) Techniques for reducing rock bottom leakage in memory
Kühn et al. Fined-grained body biasing for frequency scaling in advanced soi processes
US10243558B2 (en) Complementary metal-oxide-semiconductor (CMOS) inverter circuit device
WO2021231384A1 (en) Low leakage core power lowering (cpe) write assist scheme

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180830

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180830

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20180830

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20180905

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20181225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190315

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190611

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190620

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190709

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190722

R150 Certificate of patent or registration of utility model

Ref document number: 6560965

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250