WO2021231384A1 - Low leakage core power lowering (cpe) write assist scheme - Google Patents

Low leakage core power lowering (cpe) write assist scheme Download PDF

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Publication number
WO2021231384A1
WO2021231384A1 PCT/US2021/031715 US2021031715W WO2021231384A1 WO 2021231384 A1 WO2021231384 A1 WO 2021231384A1 US 2021031715 W US2021031715 W US 2021031715W WO 2021231384 A1 WO2021231384 A1 WO 2021231384A1
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WIPO (PCT)
Prior art keywords
switch
column selection
memory
memory control
supply voltage
Prior art date
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PCT/US2021/031715
Other languages
French (fr)
Inventor
Adithya Bhaskaran
Pradeep Raj
Rahul Sahu
Sharad Kumar Gupta
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Qualcomm Incorporated
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Publication date
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Publication of WO2021231384A1 publication Critical patent/WO2021231384A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • the teachings of the present disclosure relate generally to electronic systems, and more particularly, to a memory device.
  • processors and memory are used extensively today in almost every electronic application.
  • the processor controls the execution of program instructions, arithmetic functions, and access to memory and peripherals.
  • the processor executes program instructions by performing one or more arithmetic functions on data stored in memory.
  • memory There are many different types of memory, which may be implemented using any of various suitable technologies.
  • the memory system generally includes a first head switch, and a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch.
  • the memory system may also include a second head switch coupled between the memory supply voltage rail and the CPL switches.
  • Certain aspects of the present disclosure are directed to a method for memory control.
  • the method generally includes coupling, via a first head switch, a memory supply voltage rail to a plurality of memory control circuits; precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; coupling, via a second head switch, the memory supply voltage rail to a CPL switch of each of the plurality of memory control circuits; and reducing a voltage of the supply voltage node for the column by controlling the CPL switch.
  • the apparatus generally includes first means for coupling a memory supply voltage rail to a plurality of memory control circuits; means for precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; second means for coupling the memory supply voltage rail to a CPL switch of each of the plurality of memory control circuits; and means for reducing a voltage of the supply voltage node for the column, the means for reducing the voltage comprising means for controlling the CPL switch.
  • FIG. 1 is an illustration of an exemplary system-on-chip (SoC) integrated circuit design, in accordance with certain aspects of the present disclosure.
  • FIG. 2 illustrates a memory control system, in accordance with certain aspects of the present disclosure.
  • FIG. 3 illustrates control circuits for implementing a core power lowering (CPL) write assist technique, in accordance with certain aspects of the present disclosure.
  • CPL core power lowering
  • FIG. 4 illustrates a gating circuit, in accordance with certain aspects of the present disclosure.
  • FIG. 5 is a flow diagram illustrating example operations for memory control, in accordance with certain aspects of the present disclosure.
  • the memory control system may be configured to implement a core power lowering (CPL) write assist technique to improve writability for memory. For example, a supply voltage for the memory may be reduced during a write phase, strengthening a pull-up path for the memory when performing a write operation.
  • CPL core power lowering
  • computing device and “mobile device” are used interchangeably herein to refer to any one or all of servers, personal computers, smartphones, cellular telephones, tablet computers, laptop computers, netbooks, ultrabooks, palm-top computers, personal data assistants (PDAs), wireless electronic mail receivers, multimedia Internet-enabled cellular telephones, Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a programmable processor.
  • PDAs personal data assistants
  • wireless electronic mail receivers multimedia Internet-enabled cellular telephones
  • GPS Global Positioning System
  • wireless gaming controllers and similar personal electronic devices which include a programmable processor.
  • While the various aspects are particularly useful in mobile devices (e.g., smartphones, laptop computers, etc.), which have limited resources (e.g., processing power, battery, size, etc.), the aspects are generally useful in any computing device that may benefit from improved processor performance and reduced energy consumption.
  • mobile devices e.g., smartphones, laptop computers, etc.
  • resources e.g., processing power, battery, size, etc.
  • the aspects are generally useful in any computing device that may benefit from improved processor performance and reduced energy consumption.
  • multicore processor is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions.
  • multiprocessor is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.
  • SoC system on chip
  • IC integrated circuit
  • a single SoC may contain circuitry for digital, analog, mixed-signal, and radio-frequency functions.
  • a single SoC may also include any number of general purpose and/or specialized processors (digital signal processors (DSPs), modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.
  • DSPs digital signal processors
  • modem processors modem processors
  • video processors etc.
  • memory blocks e.g., ROM, RAM, flash, etc.
  • resources e.g., timers, voltage regulators, oscillators, etc.
  • Memory technologies described herein may be suitable for storing instructions, programs, control signals, and/or data for use in or by a computer or other digital electronic device. Any references to terminology and/or technical details related to an individual type of memory, interface, standard, or memory technology are for illustrative purposes only, and not intended to limit the scope of the claims to a particular memory system or technology unless specifically recited in the claim language.
  • Mobile computing device architectures have grown in complexity, and now commonly include multiple processor cores, SoCs, co-processors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnections (e.g., buses and/or fabrics), and numerous other resources that execute complex and power intensive software applications (e.g., video streaming applications, etc.).
  • processors e.g., communication modem chips, GPS receivers, etc.
  • complex memory systems e.g., intricate electrical interconnections (e.g., buses and/or fabrics), and numerous other resources that execute complex and power intensive software applications (e.g., video streaming applications, etc.).
  • FIG. 1 illustrates example components and interconnections in a system-on- chip (SoC) 100 suitable for implementing various aspects of the present disclosure.
  • the SoC 100 may include a number of heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108.
  • processors 102, 104, 106, 108 may include one or more cores, and each processor/core may perform operations independent of the other processors/cores.
  • the processors 102, 104, 106, 108 may be organized in close proximity to one another (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at a much higher frequency/clock rate than would be possible if the signals were to travel off-chip.
  • the proximity of the cores may also allow for the sharing of on-chip memory and resources (e.g., voltage rails), as well as for more coordinated cooperation between cores.
  • the SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversions, and/or wireless data transmissions, and for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.).
  • System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and/or other similar components used to support the processors and software clients running on the computing device.
  • the system components and resources 110 may also include circuitry for interfacing with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.
  • the SoC 100 may further include a Universal Serial Bus (USB) controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116.
  • the SoC 100 may also include an input/output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.
  • the processors 102, 104, 106, 108 may be interconnected to the USB controller 112, the memory controller 114, system components and resources 110, CRM 116, and/or other system components via an interconnection/bus module 122, which may include an array of reconfigurable logic gates and/or implement a bus architecture (e.g., CoreConnect, AMBA, etc.). Communications may also be provided by advanced interconnects, such as high performance networks on chip (NoCs).
  • NoCs high performance networks on chip
  • the interconnection/bus module 122 may include or provide a bus mastering system configured to grant SoC components (e.g., processors, peripherals, etc.) exclusive control of the bus (e.g., to transfer data in burst mode, block transfer mode, etc.) for a set duration, number of operations, number of bytes, etc.
  • SoC components e.g., processors, peripherals, etc.
  • the interconnection/bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously.
  • the memory controller 114 may be a specialized hardware module configured to manage the flow of data to and from a memory 124 via a memory interface/bus 126.
  • the memory controller 114 may include control circuitry for implementing a core power lowering (CPL) write assist scheme, as described in more detail herein.
  • the memory 124 may be a static random access memory (SRAM).
  • the memory controller 114 may comprise one or more processors configured to perform read and write operations with the memory 124.
  • processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure.
  • DSPs digital signal processors
  • FPGAs field programmable gate arrays
  • PLDs programmable logic devices
  • state machines gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure.
  • the memory 124 may be part of the SoC 100.
  • Certain aspects of the present disclosure are generally directed to a low leakage current core power lowering (CPL) write assist technique.
  • the CPL write assist technique involves lowering a supply voltage applied to a memory cell when performing a write operation, allowing for a stronger pull-up path to assist writing of data to the memory (e.g., memory 124).
  • Conventional circuitry for implementing CPL write assist may include two head switches for each column of the memory 124. Given the high density of memory cells and relatively high number of columns in memory, a large number of head switches may be included for CPL write assist in conventional memory systems.
  • RBSC rock bottom sleep current
  • Certain aspects of the present disclosure are directed to circuitry for implementing CPL write assist with a reduced number of head switches as compared to conventional implementations.
  • FIG. 2 illustrates a memory control system 200, in accordance with certain aspects of the present disclosure.
  • the memory control system 200 includes memory control circuits 206, 208, 210, 212, each for generating a core voltage rail for a respective column of the memory 124.
  • the core voltage rails serve as supply voltages for the columns of the memory 124.
  • the memory control circuit 206 generates vddhx_core ⁇ 0> for column 0 of the memory 124
  • the memory control circuit 208 generates vddhx_core ⁇ l> for column 1 of the memory 124
  • the memory control circuit 210 generates vddhx_core ⁇ 2> for column 2 of the memory 124
  • the memory control circuit 212 generates vddhx_core ⁇ 3> for column 3 of the memory 124.
  • Vddhx_core ⁇ 0>, vddhx_core ⁇ l>, vddhx_core ⁇ 2>, vddhx_core ⁇ 3> are collectively referred to herein as “vddhx core.” While the memory control system 200 is illustrating memory control circuitry for four columns of memory to facilitate understanding, the aspects described herein may be implemented for memory with any number of columns. As illustrated, the memory control system 200 includes a head switch 202 between a memory supply voltage rail (e.g., referred to herein as “vddmx”) and another voltage rail node (referred to herein as “vddhx 204”) that is common to the columns of the memory 124.
  • vddmx memory supply voltage rail
  • vddhx 204 another voltage rail node
  • each of the memory control circuits 206, 208, 210, 212 includes a top disable switch 214, 216, 218, 220 (e.g., each implemented using a p-type metal-oxide-semiconductor (PMOS) transistor) and a bottom disable switch 222, 224, 226, 228 (e.g., each implemented using an n-type metal-oxide-semiconductor (NMOS) transistor), respectively.
  • the top and bottom disable switches may be controlled by a disable signal such that the bottom disable switches are closed (or open) and the top disable switches are open (or closed) when the disable signal is logic high (or logic low).
  • each of the memory control circuits 206, 208, 210, 212 includes a top column selection switch 230, 232, 234, 236 (e.g., each implemented using a PMOS transistor) and a bottom column selection switch 238, 240, 242, 244 (e.g., each implemented using a PMOS transistor), respectively.
  • the top column selection switches 230, 232, 234, 236 are controlled via respective column selection signals (also referred to as “mux selection signals”) wm ⁇ 0>, wm ⁇ l>, wm ⁇ 2>, and wm ⁇ 3>, and the bottom column selection switches are controlled via respective complementary column selection signals wm_n ⁇ 0>, wm_n ⁇ 1>, wm_n ⁇ 2>, and wm_n ⁇ 3>, as illustrated.
  • the top column selection switches 230, 232, 234, 236 may be configured to have different switch states than a respective one of the bottom column selection switches 238, 240, 242, 244.
  • the disable signal is set to logic low.
  • the top disable switches 214, 216, 218, 220 and one of the top column selection switches 230, 232, 234, 236 for the selected column are closed.
  • the bottom disable switches 222, 224, 226, 228 and one of the bottom column selection switches 238, 240, 242, 244 for the selected column are open.
  • the head switch 202 is closed such that vddhx core of the selected column is precharged via vddmx.
  • a write phase for the selected one of the columns 0-3 may begin.
  • the voltage of the core voltage rail of the selected column for the write phase may be reduced to improve writability.
  • a head switch 246 also referred to a “sleep core switch” may be coupled between vddmx and a voltage rail (referred to herein as “vdd hx common”) that is common across the control circuits 206, 208, 210, 212.
  • the sleep core switch 246 is controlled via a sleep core signal (slp core) that is logic low during a retention mode of the memory system, such that the head switch 246 (e.g., implemented by a PMOS transistor) is closed. During retention mode, data stored in the memory 124 is retained.
  • Each of the memory control circuits 206, 208, 210, 212 may include a sleep column select switch 248, 250, 252, 254 (also referred to herein as a “CPL switch”) controlled via a respective sleep column select signal wm_n_slp ⁇ 0>, wm_n_slp ⁇ l>, wm_n_slp ⁇ 2>, and wm_n_slp ⁇ 3>, as illustrated.
  • each of the memory control circuits 206, 208, 210, 212 includes a direct-current (DC) path to electric ground (or another reference potential node for the memory control system 200), allowing for respective core voltage rails to be reduced before a write phase begins.
  • memory control circuit 206 includes a DC path 290 to electric ground through the head switch 246, sleep column select switch 248, column selection switch 238, and disable switch 222.
  • FIG. 3 illustrates the memory control circuits 206, 208 for implementing CPL write assist for column 0, in accordance with certain aspects of the present disclosure.
  • the sleep column select switch 248 may be closed (e.g., wm_n_slp ⁇ 0> is set to logic low), and the sleep column select switches 250, 252, 254 may be open (sleep column select switches 252, 254 are shown in FIG. 2).
  • the head switch 246, bottom column selection switch 238, and bottom disable switch 222 are closed.
  • a current 302 flows from vddmx, through the head switch 246, the sleep column select switch 248, the bottom column selection switch 238, and the bottom disable switch 222, as illustrated.
  • the size of the transistor for implementing the bottom column selection switch 238 may be configured to be larger than the transistor for implementing the sleep column select switch 248 (e.g., the on-resistance of switch 238 may be lower than that of switch 248), resulting in vddhx_core ⁇ 0> being reduced prior to the write phase for column 0 to implement the CPL write assist technique described herein.
  • the sleep column select switches 250, 252, 254 may be open during the write phase for column 0, and current may not be sunk from the vddhx_core_common by the memory control circuits 208, 210, 212 (e.g., memory control circuits 219, 212 are shown in FIG. 2). Therefore, vddhx_core ⁇ l>, vddhx_core ⁇ 2>, vddhx_core ⁇ 3> may be maintained at a voltage such that data stored in memory cells for columns 1-3 are not disturbed. For example, vddhx_core ⁇ l> may be held high through the column selection switch 232 and the head switch 202.
  • a relatively large storage capacitive element (e.g., 50 pF) may be implemented to hold vddhx at a relatively stable voltage during the CPL write assist phase for column 0, such that the data stored in memory cells for other columns (columns 1-3) are not disturbed.
  • the head switch 202 may be controlled via a sleep periphery signal (referred to as “slp peri”).
  • Slp peri may be controlled by periphery circuitry and is logic high when the memory 124 is to be in a retention mode of operation, during which data in the memory 124 is to be retained.
  • FIG. 4 illustrates a head switch 402 coupled to gating circuits 460, 462, 464, 466, in accordance with certain aspects of the present disclosure.
  • vddhx core shown in FIGs. 2 and 3
  • wm_n_slp ⁇ 0>, wm_n_slp ⁇ l>, wm_n_slp ⁇ 2>, and wm_n_slp ⁇ 3> may be gated with a sleep word line (WL) signal (referred to herein as “slp_wl”) that is logic high during retention mode.
  • WL sleep word line
  • wm_n_slp ⁇ 0>, wm_n_slp ⁇ l>, wm_n_slp ⁇ 2>, and wm_n_slp ⁇ 3> may be set to logic low during retention mode to facilitate retention of data in memory.
  • the head switch 402 may be coupled between vddmx and a node 450 that is coupled to sources of PMOS transistors 412, 416, 420, 424 of the gating circuits.
  • Wm_n_slp ⁇ 0>, wm_n_slp ⁇ l>, wm_n_slp ⁇ 2>, and wm_n_slp ⁇ 3> may be generated at drains of respective transistors 412, 416, 420, 424 for controlling respective sleep column select switches 248, 250, 252, 254 as described with respect to FIG. 2.
  • NMOS transistors 414, 418, 422, 426 are coupled between drains of respective transistors 412, 416, 420, 424 and electric ground (a reference potential node).
  • the gates of transistors 414, 418, 422, 426 are controlled via respective column selection signals wm ⁇ 0>, wm ⁇ l>, wm ⁇ 2>, and wm ⁇ 3>, as illustrated.
  • NMOS transistors 404, 406, 408, 410 may also be coupled between the drains of respective transistors 412, 416, 420, 424 and electric ground.
  • the gates of transistors 404, 406, 408, 410 are also controlled via slp_wl. As described, slp_wl is logic high during retention mode. Therefore, transistors 404, 406, 408, 410 are turned on, and wm_n_slp ⁇ 0>, wm_n_slp ⁇ l>, wm_n_slp ⁇ 2>, and wm_n_slp ⁇ 3> are pulled to logic low, during retention mode.
  • sleep column select switches 248, 250, 252, 254 are turned on during retention mode, ensuring that vddhx core is maintained at a voltage level sufficient for retaining data stored in memory.
  • FIG. 5 is a flow diagram illustrating example operations 500 for memory control, in accordance with certain aspects of the present disclosure.
  • the operations 500 may be performed via a memory control system, such as the memory control system 200
  • the operations 500 begin, at block 502, with the memory control system coupling, via a first head switch (e.g., head switch 202), a memory supply voltage rail (e.g., vddmx) to a plurality of memory control circuits (e.g., memory control circuits 206, 208, 210, 212).
  • the memory control system precharges a supply voltage node (e.g., vddhx_core ⁇ 0>) for a column (e.g., column 0) of a memory by controlling a first column selection switch (e.g., column selection switch 230) and a second column selection switch (e.g., column selection switch 238) of each of the plurality of memory control circuits.
  • the memory control system couples, via a second head switch (e.g., head switch 246), the memory supply voltage rail to a CPL switch (e.g., sleep column select switch 248) of each of the plurality of memory control circuits, and at block 508, reduces a voltage of the supply voltage node for the column by controlling the CPL switch.
  • a second head switch e.g., head switch 246
  • the memory supply voltage rail to a CPL switch (e.g., sleep column select switch 248) of each of the plurality of memory control circuits
  • the first column selection switch (e.g., column selection switch 230) is coupled between the first head switch and the supply voltage node
  • the second column selection switch (e.g., column selection switch 238) is coupled between the supply voltage node and an electric ground.
  • precharging the supply voltage node for the column may include closing the first column selection switch and opening the second column selection switch of a respective one of the plurality of memory control circuits.
  • the memory control system may disable or enable the plurality of memory control circuits by controlling a first disable switch (e.g., top disable switch 214) coupled in parallel with the first column selection switch, and by controlling a second disable switch (e.g., bottom disable switch 222) coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
  • a first disable switch e.g., top disable switch 214
  • a second disable switch e.g., bottom disable switch 222
  • disabling the plurality of memory control circuits may include opening the first disable switch and closing the second disable switch.
  • the memory control system may close the CPL switch (e.g., sleep column select switch 248) during a retention mode of operation.
  • the memory control system may couple — via a gating switch (e.g., transistor 404) of each of the plurality of memory control circuits — a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
  • the memory control system may couple, via a third head switch (e.g., head switch 402), the memory supply voltage rail to column selection switches (e.g., transistors 412, 414) of the plurality of memory control circuits, and control, via the column selection switches, the CPL switches when the gating switches are open.
  • a memory control system comprising: a first head switch; a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch; and a second head switch coupled between the memory supply voltage rail and the CPL switches.
  • CPL core power lowering
  • Aspect 2 The memory control system of aspect 1, wherein the first column selection switch and the second column selection switch are configured to have different switch states.
  • each of the plurality of memory control circuits further comprises: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
  • Aspect 4 The memory control system of aspect 3, wherein the first disable switch and the second disable switch are configured to have different switch states.
  • Aspect 5 The memory control system of any one of aspects 1-4, wherein the CPL switch is configured to be closed during a retention mode of operation of the memory control system.
  • each of the plurality of memory control circuits comprises a gating circuit having a gating switch coupled between a control input of the CPL switch and the electric ground, the gating switch being closed during a retention mode of operation of the memory control system.
  • Aspect 7 The memory control system of aspect 6, further comprising a third head switch, wherein each of the gating circuits further comprises: a third column selection switch, wherein the third head switch is coupled between the memory supply voltage rail and the third column selection switch; and a fourth column selection switch coupled between the third column selection switch and the electric ground, the control input of the CPL switch being coupled to a node between the third column selection switch and the fourth column selection switch.
  • a method for memory control comprising: coupling, via a first head switch, a memory supply voltage rail to a plurality of memory control circuits; precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; coupling, via a second head switch, the memory supply voltage rail to a core power lowering (CPL) switch of each of the plurality of memory control circuits; and reducing a voltage of the supply voltage node for the column by controlling the CPL switch.
  • CPL core power lowering
  • Aspect 9 The method of aspect 8, wherein: the first column selection switch is coupled between the first head switch and the supply voltage node; the second column selection switch is coupled between the supply voltage node and an electric ground; and precharging the supply voltage node for the column comprises closing the first column selection switch and opening the second column selection switch of a respective one of the plurality of memory control circuits.
  • Aspect 10 The method of aspect 9, further comprising disabling or enabling the plurality of memory control circuits by controlling: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
  • Aspect 11 The method of aspect 10, wherein disabling the plurality of memory control circuits comprises opening the first disable switch and closing the second disable switch.
  • Aspect 12 The method of any one of aspects 8-11, further comprising closing the CPL switch during a retention mode of operation.
  • Aspect 13 The method of any one of aspects 8-12, further comprising coupling, via a gating switch of each of the plurality of memory control circuits, a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
  • Aspect 14 The method of aspect 13, further comprising: coupling, via a third head switch, the memory supply voltage rail to column selection switches of the plurality of memory control circuits; and controlling, via the column selection switches, the CPL switches when the gating switches are open.
  • An apparatus for memory control comprising: first means for coupling a memory supply voltage rail to a plurality of memory control circuits; means for precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; second means for coupling the memory supply voltage rail to a core power lowering (CPL) switch of each of the plurality of memory control circuits; and means for reducing a voltage of the supply voltage node for the column, the means for reducing the voltage comprising means for controlling the CPL switch.
  • CPL core power lowering
  • Aspect 16 The apparatus of aspect 15, wherein: the first column selection switch is coupled between the first means for coupling and the supply voltage node; the second column selection switch is coupled between the supply voltage node and an electric ground; and the means for precharging the supply voltage node for the column comprises means for closing the first column selection switch and means for opening the second column selection switch of a respective one of the plurality of memory control circuits.
  • Aspect 17 The apparatus of aspect 16, further comprising means for disabling or enabling the plurality of memory control circuits by controlling: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
  • Aspect 18 The apparatus of aspect 17, wherein the means for disabling or enabling is configured to disable the plurality of memory control circuits by opening the first disable switch and closing the second disable switch.
  • Aspect 19 The apparatus of any one of aspects 15-18, further comprising means for closing the CPL switch during a retention mode of operation.
  • Aspect 20 The apparatus of any one of aspects 15-19, further comprising means for coupling a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
  • the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation.
  • the term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another — even if objects A and C do not directly physically touch each other.
  • circuit and circuitry are used broadly and intended to include both hardware implementations of electrical devices and conductors that, when connected and configured, enable the performance of the functions described in the present disclosure, without limitation as to the type of electronic circuits.
  • circuitry are used broadly and intended to include both hardware implementations of electrical devices and conductors that, when connected and configured, enable the performance of the functions described in the present disclosure, without limitation as to the type of electronic circuits.
  • One or more of the components, steps, features, and/or functions illustrated herein may be rearranged and/or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from features disclosed herein.
  • the apparatus, devices, and/or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein.
  • the algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
  • “at least one of: a, />, or c” is intended to cover at least: a, Z>, c, a-b , a-c, b-c , and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b- b-c , c-c, and c-c-c or any other ordering of a, Z>, and c).
  • means for disabling, means for enabling, means for reducing, means for precharging, and/or means for coupling may include a switch (e.g., implemented by one or more transistors), such as the head switch 202, head switch 246, head switch 402, disable switches 214, 216, 218, 220, CPL switches 248, 250, 252, 254, and/or gating switch 404, 406, 408, 410.
  • Means for opening, and/or means for precharging may include a memory controller such as the memory controller 114.

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Abstract

Memory system configured to perform write assist, the memory system including: a first head switch, a second head switch and a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch. The second head switch is coupled between the memory supply voltage rail and the CPL switches. The first and second head switches are directly coupled between the memory supply voltage rail and respective voltage rail nodes which are common to all memory control circuits in the plurality of memory control circuits.

Description

LOW LEAKAGE CORE POWER LOWERING (CPL) WRITE ASSIST
SCHEME
CROSS REFERENCE TO RELATED APPLICATION [0001] This Application claims priority to India Provisional Patent Application No. 202041020380, filed May 14, 2020, the content of which is incorporated herein in its entirety.
FIELD OF THE DISCLOSURE
[0002] The teachings of the present disclosure relate generally to electronic systems, and more particularly, to a memory device.
BACKGROUND
[0003] Electronic devices including processors and memory are used extensively today in almost every electronic application. The processor controls the execution of program instructions, arithmetic functions, and access to memory and peripherals. In the simplest form, the processor executes program instructions by performing one or more arithmetic functions on data stored in memory. There are many different types of memory, which may be implemented using any of various suitable technologies.
SUMMARY
[0004] The following presents a simplified summary of one or more aspects of the present disclosure, in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.
[0005] Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a first head switch, and a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch. The memory system may also include a second head switch coupled between the memory supply voltage rail and the CPL switches.
[0006] Certain aspects of the present disclosure are directed to a method for memory control. The method generally includes coupling, via a first head switch, a memory supply voltage rail to a plurality of memory control circuits; precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; coupling, via a second head switch, the memory supply voltage rail to a CPL switch of each of the plurality of memory control circuits; and reducing a voltage of the supply voltage node for the column by controlling the CPL switch.
[0007] Certain aspects of the present disclosure are directed to an apparatus for memory control. The apparatus generally includes first means for coupling a memory supply voltage rail to a plurality of memory control circuits; means for precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; second means for coupling the memory supply voltage rail to a CPL switch of each of the plurality of memory control circuits; and means for reducing a voltage of the supply voltage node for the column, the means for reducing the voltage comprising means for controlling the CPL switch.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.
[0009] FIG. 1 is an illustration of an exemplary system-on-chip (SoC) integrated circuit design, in accordance with certain aspects of the present disclosure. [0010] FIG. 2 illustrates a memory control system, in accordance with certain aspects of the present disclosure.
[0011] FIG. 3 illustrates control circuits for implementing a core power lowering (CPL) write assist technique, in accordance with certain aspects of the present disclosure.
[0012] FIG. 4 illustrates a gating circuit, in accordance with certain aspects of the present disclosure.
[0013] FIG. 5 is a flow diagram illustrating example operations for memory control, in accordance with certain aspects of the present disclosure.
DETAILED DESCRIPTION
[0014] Certain aspects of the present disclosure are generally directed to a memory control system. The memory control system may be configured to implement a core power lowering (CPL) write assist technique to improve writability for memory. For example, a supply voltage for the memory may be reduced during a write phase, strengthening a pull-up path for the memory when performing a write operation.
[0015] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
[0016] The various aspects will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the disclosure or the claims. [0017] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any one or all of servers, personal computers, smartphones, cellular telephones, tablet computers, laptop computers, netbooks, ultrabooks, palm-top computers, personal data assistants (PDAs), wireless electronic mail receivers, multimedia Internet-enabled cellular telephones, Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a programmable processor. While the various aspects are particularly useful in mobile devices (e.g., smartphones, laptop computers, etc.), which have limited resources (e.g., processing power, battery, size, etc.), the aspects are generally useful in any computing device that may benefit from improved processor performance and reduced energy consumption.
[0018] The term “multicore processor” is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term “multiprocessor” is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.
[0019] The term “system on chip” (SoC) is used herein to refer to a single integrated circuit (IC) chip that contains multiple resources and/or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio-frequency functions. A single SoC may also include any number of general purpose and/or specialized processors (digital signal processors (DSPs), modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.
[0020] Memory technologies described herein may be suitable for storing instructions, programs, control signals, and/or data for use in or by a computer or other digital electronic device. Any references to terminology and/or technical details related to an individual type of memory, interface, standard, or memory technology are for illustrative purposes only, and not intended to limit the scope of the claims to a particular memory system or technology unless specifically recited in the claim language. Mobile computing device architectures have grown in complexity, and now commonly include multiple processor cores, SoCs, co-processors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnections (e.g., buses and/or fabrics), and numerous other resources that execute complex and power intensive software applications (e.g., video streaming applications, etc.).
EXAMPLE SoC
[0021] FIG. 1 illustrates example components and interconnections in a system-on- chip (SoC) 100 suitable for implementing various aspects of the present disclosure. The SoC 100 may include a number of heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108, may include one or more cores, and each processor/core may perform operations independent of the other processors/cores. The processors 102, 104, 106, 108 may be organized in close proximity to one another (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at a much higher frequency/clock rate than would be possible if the signals were to travel off-chip. The proximity of the cores may also allow for the sharing of on-chip memory and resources (e.g., voltage rails), as well as for more coordinated cooperation between cores.
[0022] The SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversions, and/or wireless data transmissions, and for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and/or other similar components used to support the processors and software clients running on the computing device. The system components and resources 110 may also include circuitry for interfacing with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.
[0023] The SoC 100 may further include a Universal Serial Bus (USB) controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. The SoC 100 may also include an input/output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.
[0024] The processors 102, 104, 106, 108 may be interconnected to the USB controller 112, the memory controller 114, system components and resources 110, CRM 116, and/or other system components via an interconnection/bus module 122, which may include an array of reconfigurable logic gates and/or implement a bus architecture (e.g., CoreConnect, AMBA, etc.). Communications may also be provided by advanced interconnects, such as high performance networks on chip (NoCs).
[0025] The interconnection/bus module 122 may include or provide a bus mastering system configured to grant SoC components (e.g., processors, peripherals, etc.) exclusive control of the bus (e.g., to transfer data in burst mode, block transfer mode, etc.) for a set duration, number of operations, number of bytes, etc. In some cases, the interconnection/bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously.
[0026] The memory controller 114 may be a specialized hardware module configured to manage the flow of data to and from a memory 124 via a memory interface/bus 126. The memory controller 114 may include control circuitry for implementing a core power lowering (CPL) write assist scheme, as described in more detail herein. In certain aspects, the memory 124 may be a static random access memory (SRAM).
[0027] The memory controller 114 may comprise one or more processors configured to perform read and write operations with the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. In certain aspects, the memory 124 may be part of the SoC 100. EXAMPLE LOW LEAKAGE CORE POWER LOWERING (CPL) WRITE ASSIST
SCHEME
[0028] Certain aspects of the present disclosure are generally directed to a low leakage current core power lowering (CPL) write assist technique. The CPL write assist technique involves lowering a supply voltage applied to a memory cell when performing a write operation, allowing for a stronger pull-up path to assist writing of data to the memory (e.g., memory 124). Conventional circuitry for implementing CPL write assist may include two head switches for each column of the memory 124. Given the high density of memory cells and relatively high number of columns in memory, a large number of head switches may be included for CPL write assist in conventional memory systems. Moreover, due to leakage current associated with each of the head switches, rock bottom sleep current (RBSC) of the memory system is increased, even when the head switches are turned off. Certain aspects of the present disclosure are directed to circuitry for implementing CPL write assist with a reduced number of head switches as compared to conventional implementations.
[0029] FIG. 2 illustrates a memory control system 200, in accordance with certain aspects of the present disclosure. The memory control system 200 includes memory control circuits 206, 208, 210, 212, each for generating a core voltage rail for a respective column of the memory 124. The core voltage rails serve as supply voltages for the columns of the memory 124. For example, the memory control circuit 206 generates vddhx_core<0> for column 0 of the memory 124, the memory control circuit 208 generates vddhx_core<l> for column 1 of the memory 124, the memory control circuit 210 generates vddhx_core<2> for column 2 of the memory 124, and the memory control circuit 212 generates vddhx_core<3> for column 3 of the memory 124. Vddhx_core<0>, vddhx_core<l>, vddhx_core<2>, vddhx_core<3> are collectively referred to herein as “vddhx core.” While the memory control system 200 is illustrating memory control circuitry for four columns of memory to facilitate understanding, the aspects described herein may be implemented for memory with any number of columns. As illustrated, the memory control system 200 includes a head switch 202 between a memory supply voltage rail (e.g., referred to herein as “vddmx”) and another voltage rail node (referred to herein as “vddhx 204”) that is common to the columns of the memory 124. [0030] As illustrated, each of the memory control circuits 206, 208, 210, 212 includes a top disable switch 214, 216, 218, 220 (e.g., each implemented using a p-type metal-oxide-semiconductor (PMOS) transistor) and a bottom disable switch 222, 224, 226, 228 (e.g., each implemented using an n-type metal-oxide-semiconductor (NMOS) transistor), respectively. The top and bottom disable switches may be controlled by a disable signal such that the bottom disable switches are closed (or open) and the top disable switches are open (or closed) when the disable signal is logic high (or logic low).
[0031] As illustrated, each of the memory control circuits 206, 208, 210, 212 includes a top column selection switch 230, 232, 234, 236 (e.g., each implemented using a PMOS transistor) and a bottom column selection switch 238, 240, 242, 244 (e.g., each implemented using a PMOS transistor), respectively. The top column selection switches 230, 232, 234, 236 are controlled via respective column selection signals (also referred to as “mux selection signals”) wm<0>, wm<l>, wm<2>, and wm<3>, and the bottom column selection switches are controlled via respective complementary column selection signals wm_n<0>, wm_n <1>, wm_n <2>, and wm_n <3>, as illustrated. In other words, the top column selection switches 230, 232, 234, 236 may be configured to have different switch states than a respective one of the bottom column selection switches 238, 240, 242, 244.
[0032] During a precharge phase of the memory system for a selected column, the disable signal is set to logic low. The top disable switches 214, 216, 218, 220 and one of the top column selection switches 230, 232, 234, 236 for the selected column are closed. Moreover, the bottom disable switches 222, 224, 226, 228 and one of the bottom column selection switches 238, 240, 242, 244 for the selected column are open. Moreover, the head switch 202 is closed such that vddhx core of the selected column is precharged via vddmx.
[0033] After the precharge phase, a write phase for the selected one of the columns 0-3 may begin. As described herein, to implement CPL write assist, the voltage of the core voltage rail of the selected column for the write phase may be reduced to improve writability. To implement CPL write assist, a head switch 246 (also referred to a “sleep core switch”) may be coupled between vddmx and a voltage rail (referred to herein as “vdd hx common”) that is common across the control circuits 206, 208, 210, 212. The sleep core switch 246 is controlled via a sleep core signal (slp core) that is logic low during a retention mode of the memory system, such that the head switch 246 (e.g., implemented by a PMOS transistor) is closed. During retention mode, data stored in the memory 124 is retained. Each of the memory control circuits 206, 208, 210, 212 may include a sleep column select switch 248, 250, 252, 254 (also referred to herein as a “CPL switch”) controlled via a respective sleep column select signal wm_n_slp<0>, wm_n_slp<l>, wm_n_slp<2>, and wm_n_slp<3>, as illustrated. Thus, each of the memory control circuits 206, 208, 210, 212 includes a direct-current (DC) path to electric ground (or another reference potential node for the memory control system 200), allowing for respective core voltage rails to be reduced before a write phase begins. For example, memory control circuit 206 includes a DC path 290 to electric ground through the head switch 246, sleep column select switch 248, column selection switch 238, and disable switch 222.
[0034] FIG. 3 illustrates the memory control circuits 206, 208 for implementing CPL write assist for column 0, in accordance with certain aspects of the present disclosure. Prior to a write phase for column 0, the sleep column select switch 248 may be closed (e.g., wm_n_slp<0> is set to logic low), and the sleep column select switches 250, 252, 254 may be open (sleep column select switches 252, 254 are shown in FIG. 2). Moreover, the head switch 246, bottom column selection switch 238, and bottom disable switch 222 are closed. Therefore, a current 302 (e.g., DC) flows from vddmx, through the head switch 246, the sleep column select switch 248, the bottom column selection switch 238, and the bottom disable switch 222, as illustrated. The size of the transistor for implementing the bottom column selection switch 238 may be configured to be larger than the transistor for implementing the sleep column select switch 248 (e.g., the on-resistance of switch 238 may be lower than that of switch 248), resulting in vddhx_core<0> being reduced prior to the write phase for column 0 to implement the CPL write assist technique described herein.
[0035] As described, the sleep column select switches 250, 252, 254 may be open during the write phase for column 0, and current may not be sunk from the vddhx_core_common by the memory control circuits 208, 210, 212 (e.g., memory control circuits 219, 212 are shown in FIG. 2). Therefore, vddhx_core<l>, vddhx_core<2>, vddhx_core<3> may be maintained at a voltage such that data stored in memory cells for columns 1-3 are not disturbed. For example, vddhx_core<l> may be held high through the column selection switch 232 and the head switch 202. In certain aspects, a relatively large storage capacitive element (e.g., 50 pF) may be implemented to hold vddhx at a relatively stable voltage during the CPL write assist phase for column 0, such that the data stored in memory cells for other columns (columns 1-3) are not disturbed.
[0036] As illustrated, the head switch 202 may be controlled via a sleep periphery signal (referred to as “slp peri”). Slp peri may be controlled by periphery circuitry and is logic high when the memory 124 is to be in a retention mode of operation, during which data in the memory 124 is to be retained.
[0037] FIG. 4 illustrates a head switch 402 coupled to gating circuits 460, 462, 464, 466, in accordance with certain aspects of the present disclosure. In certain aspects, in order for vddhx core (shown in FIGs. 2 and 3) to be maintained at a voltage level sufficient for retaining data stored in memory during retention mode, wm_n_slp<0>, wm_n_slp<l>, wm_n_slp<2>, and wm_n_slp<3> may be gated with a sleep word line (WL) signal (referred to herein as “slp_wl”) that is logic high during retention mode. Accordingly, wm_n_slp<0>, wm_n_slp<l>, wm_n_slp<2>, and wm_n_slp<3> may be set to logic low during retention mode to facilitate retention of data in memory. For example, the head switch 402 may be coupled between vddmx and a node 450 that is coupled to sources of PMOS transistors 412, 416, 420, 424 of the gating circuits. Wm_n_slp<0>, wm_n_slp<l>, wm_n_slp<2>, and wm_n_slp<3> may be generated at drains of respective transistors 412, 416, 420, 424 for controlling respective sleep column select switches 248, 250, 252, 254 as described with respect to FIG. 2. As illustrated, NMOS transistors 414, 418, 422, 426 are coupled between drains of respective transistors 412, 416, 420, 424 and electric ground (a reference potential node). The gates of transistors 414, 418, 422, 426 are controlled via respective column selection signals wm<0>, wm<l>, wm<2>, and wm<3>, as illustrated.
[0038] NMOS transistors 404, 406, 408, 410 may also be coupled between the drains of respective transistors 412, 416, 420, 424 and electric ground. The gates of transistors 404, 406, 408, 410 are also controlled via slp_wl. As described, slp_wl is logic high during retention mode. Therefore, transistors 404, 406, 408, 410 are turned on, and wm_n_slp<0>, wm_n_slp<l>, wm_n_slp<2>, and wm_n_slp<3> are pulled to logic low, during retention mode. Thus, as illustrated in FIG. 2, sleep column select switches 248, 250, 252, 254 are turned on during retention mode, ensuring that vddhx core is maintained at a voltage level sufficient for retaining data stored in memory.
[0039] FIG. 5 is a flow diagram illustrating example operations 500 for memory control, in accordance with certain aspects of the present disclosure. The operations 500 may be performed via a memory control system, such as the memory control system 200
[0040] The operations 500 begin, at block 502, with the memory control system coupling, via a first head switch (e.g., head switch 202), a memory supply voltage rail (e.g., vddmx) to a plurality of memory control circuits (e.g., memory control circuits 206, 208, 210, 212). At block 504, the memory control system precharges a supply voltage node (e.g., vddhx_core<0>) for a column (e.g., column 0) of a memory by controlling a first column selection switch (e.g., column selection switch 230) and a second column selection switch (e.g., column selection switch 238) of each of the plurality of memory control circuits. At block 506, the memory control system couples, via a second head switch (e.g., head switch 246), the memory supply voltage rail to a CPL switch (e.g., sleep column select switch 248) of each of the plurality of memory control circuits, and at block 508, reduces a voltage of the supply voltage node for the column by controlling the CPL switch.
[0041] In certain aspects, the first column selection switch (e.g., column selection switch 230) is coupled between the first head switch and the supply voltage node, and the second column selection switch (e.g., column selection switch 238) is coupled between the supply voltage node and an electric ground. In certain aspects, precharging the supply voltage node for the column may include closing the first column selection switch and opening the second column selection switch of a respective one of the plurality of memory control circuits. In some cases, the memory control system may disable or enable the plurality of memory control circuits by controlling a first disable switch (e.g., top disable switch 214) coupled in parallel with the first column selection switch, and by controlling a second disable switch (e.g., bottom disable switch 222) coupled in series with the second column selection switch and between the supply voltage node and the electric ground. For example, disabling the plurality of memory control circuits may include opening the first disable switch and closing the second disable switch.
[0042] In certain aspects, the memory control system may close the CPL switch (e.g., sleep column select switch 248) during a retention mode of operation. In certain aspects, the memory control system may couple — via a gating switch (e.g., transistor 404) of each of the plurality of memory control circuits — a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches. In some cases, the memory control system may couple, via a third head switch (e.g., head switch 402), the memory supply voltage rail to column selection switches (e.g., transistors 412, 414) of the plurality of memory control circuits, and control, via the column selection switches, the CPL switches when the gating switches are open.
Example Aspects
[0043] Aspect 1. A memory control system comprising: a first head switch; a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch; and a second head switch coupled between the memory supply voltage rail and the CPL switches.
[0044] Aspect 2. The memory control system of aspect 1, wherein the first column selection switch and the second column selection switch are configured to have different switch states.
[0045] Aspect 3. The memory control system of any one of aspects 1-2, wherein each of the plurality of memory control circuits further comprises: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground. [0046] Aspect 4. The memory control system of aspect 3, wherein the first disable switch and the second disable switch are configured to have different switch states.
[0047] Aspect 5. The memory control system of any one of aspects 1-4, wherein the CPL switch is configured to be closed during a retention mode of operation of the memory control system.
[0048] Aspect 6. The memory control system of any one of aspects 1-5, wherein each of the plurality of memory control circuits comprises a gating circuit having a gating switch coupled between a control input of the CPL switch and the electric ground, the gating switch being closed during a retention mode of operation of the memory control system.
[0049] Aspect 7. The memory control system of aspect 6, further comprising a third head switch, wherein each of the gating circuits further comprises: a third column selection switch, wherein the third head switch is coupled between the memory supply voltage rail and the third column selection switch; and a fourth column selection switch coupled between the third column selection switch and the electric ground, the control input of the CPL switch being coupled to a node between the third column selection switch and the fourth column selection switch.
[0050] Aspect 8. A method for memory control, comprising: coupling, via a first head switch, a memory supply voltage rail to a plurality of memory control circuits; precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; coupling, via a second head switch, the memory supply voltage rail to a core power lowering (CPL) switch of each of the plurality of memory control circuits; and reducing a voltage of the supply voltage node for the column by controlling the CPL switch.
[0051] Aspect 9. The method of aspect 8, wherein: the first column selection switch is coupled between the first head switch and the supply voltage node; the second column selection switch is coupled between the supply voltage node and an electric ground; and precharging the supply voltage node for the column comprises closing the first column selection switch and opening the second column selection switch of a respective one of the plurality of memory control circuits. [0052] Aspect 10. The method of aspect 9, further comprising disabling or enabling the plurality of memory control circuits by controlling: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
[0053] Aspect 11. The method of aspect 10, wherein disabling the plurality of memory control circuits comprises opening the first disable switch and closing the second disable switch.
[0054] Aspect 12. The method of any one of aspects 8-11, further comprising closing the CPL switch during a retention mode of operation.
[0055] Aspect 13. The method of any one of aspects 8-12, further comprising coupling, via a gating switch of each of the plurality of memory control circuits, a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
[0056] Aspect 14. The method of aspect 13, further comprising: coupling, via a third head switch, the memory supply voltage rail to column selection switches of the plurality of memory control circuits; and controlling, via the column selection switches, the CPL switches when the gating switches are open.
[0057] Aspect 15. An apparatus for memory control, comprising: first means for coupling a memory supply voltage rail to a plurality of memory control circuits; means for precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; second means for coupling the memory supply voltage rail to a core power lowering (CPL) switch of each of the plurality of memory control circuits; and means for reducing a voltage of the supply voltage node for the column, the means for reducing the voltage comprising means for controlling the CPL switch.
[0058] Aspect 16. The apparatus of aspect 15, wherein: the first column selection switch is coupled between the first means for coupling and the supply voltage node; the second column selection switch is coupled between the supply voltage node and an electric ground; and the means for precharging the supply voltage node for the column comprises means for closing the first column selection switch and means for opening the second column selection switch of a respective one of the plurality of memory control circuits.
[0059] Aspect 17. The apparatus of aspect 16, further comprising means for disabling or enabling the plurality of memory control circuits by controlling: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
[0060] Aspect 18. The apparatus of aspect 17, wherein the means for disabling or enabling is configured to disable the plurality of memory control circuits by opening the first disable switch and closing the second disable switch.
[0061] Aspect 19. The apparatus of any one of aspects 15-18, further comprising means for closing the CPL switch during a retention mode of operation.
[0062] Aspect 20. The apparatus of any one of aspects 15-19, further comprising means for coupling a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
[0063] Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another — even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly physically in contact with the second object. The terms “circuit” and “circuitry” are used broadly and intended to include both hardware implementations of electrical devices and conductors that, when connected and configured, enable the performance of the functions described in the present disclosure, without limitation as to the type of electronic circuits. [0064] The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using hardware, for example.
[0065] One or more of the components, steps, features, and/or functions illustrated herein may be rearranged and/or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from features disclosed herein. The apparatus, devices, and/or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein. The algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
[0066] It is to be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.
[0067] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. A phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, />, or c” is intended to cover at least: a, Z>, c, a-b , a-c, b-c , and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b- b-c , c-c, and c-c-c or any other ordering of a, Z>, and c). All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.” For example, means for disabling, means for enabling, means for reducing, means for precharging, and/or means for coupling may include a switch (e.g., implemented by one or more transistors), such as the head switch 202, head switch 246, head switch 402, disable switches 214, 216, 218, 220, CPL switches 248, 250, 252, 254, and/or gating switch 404, 406, 408, 410. Means for opening, and/or means for precharging may include a memory controller such as the memory controller 114.
[0068] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

CLAIMS What is claimed is:
1. A memory control system comprising: a first head switch; a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch; and a second head switch coupled between the memory supply voltage rail and the CPL switches.
2. The memory control system of claim 1, wherein the first column selection switch and the second column selection switch are configured to have different switch states.
3. The memory control system of claim 1, wherein each of the plurality of memory control circuits further comprises: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
4. The memory control system of claim 3, wherein the first disable switch and the second disable switch are configured to have different switch states.
5. The memory control system of claim 1, wherein the CPL switch is configured to be closed during a retention mode of operation of the memory control system.
6. The memory control system of claim 1, wherein each of the plurality of memory control circuits comprises a gating circuit having a gating switch coupled between a control input of the CPL switch and the electric ground, the gating switch being closed during a retention mode of operation of the memory control system.
7. The memory control system of claim 6, further comprising a third head switch, wherein each of the gating circuits further comprises: a third column selection switch, wherein the third head switch is coupled between the memory supply voltage rail and the third column selection switch; and a fourth column selection switch coupled between the third column selection switch and the electric ground, the control input of the CPL switch being coupled to a node between the third column selection switch and the fourth column selection switch.
8. A method for memory control, comprising: coupling, via a first head switch, a memory supply voltage rail to a plurality of memory control circuits; precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; coupling, via a second head switch, the memory supply voltage rail to a core power lowering (CPL) switch of each of the plurality of memory control circuits; and reducing a voltage of the supply voltage node for the column by controlling the CPL switch.
9. The method of claim 8, wherein: the first column selection switch is coupled between the first head switch and the supply voltage node; the second column selection switch is coupled between the supply voltage node and an electric ground; and precharging the supply voltage node for the column comprises closing the first column selection switch and opening the second column selection switch of a respective one of the plurality of memory control circuits.
10. The method of claim 9, further comprising disabling or enabling the plurality of memory control circuits by controlling: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
11. The method of claim 10, wherein disabling the plurality of memory control circuits comprises opening the first disable switch and closing the second disable switch.
12. The method of claim 8, further comprising closing the CPL switch during a retention mode of operation.
13. The method of claim 8, further comprising coupling, via a gating switch of each of the plurality of memory control circuits, a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
14. The method of claim 13, further comprising: coupling, via a third head switch, the memory supply voltage rail to column selection switches of the plurality of memory control circuits; and controlling, via the column selection switches, the CPL switches when the gating switches are open.
15. An apparatus for memory control, comprising: first means for coupling a memory supply voltage rail to a plurality of memory control circuits; means for precharging a supply voltage node for a column of a memory by controlling a first column selection switch and a second column selection switch of each of the plurality of memory control circuits; second means for coupling the memory supply voltage rail to a core power lowering (CPL) switch of each of the plurality of memory control circuits; and means for reducing a voltage of the supply voltage node for the column, the means for reducing the voltage comprising means for controlling the CPL switch.
16. The apparatus of claim 15, wherein: the first column selection switch is coupled between the first means for coupling and the supply voltage node; the second column selection switch is coupled between the supply voltage node and an electric ground; and the means for precharging the supply voltage node for the column comprises means for closing the first column selection switch and means for opening the second column selection switch of a respective one of the plurality of memory control circuits.
17. The apparatus of claim 16, further comprising means for disabling or enabling the plurality of memory control circuits by controlling: a first disable switch coupled in parallel with the first column selection switch; and a second disable switch coupled in series with the second column selection switch and between the supply voltage node and the electric ground.
18. The apparatus of claim 17, wherein the means for disabling or enabling is configured to disable the plurality of memory control circuits by opening the first disable switch and closing the second disable switch.
19. The apparatus of claim 15, further comprising means for closing the CPL switch during a retention mode of operation.
20. The apparatus of claim 15, further comprising means for coupling a control input of the CPL switches to electric ground during a retention mode of operation by closing the CPL switches.
PCT/US2021/031715 2020-05-14 2021-05-11 Low leakage core power lowering (cpe) write assist scheme WO2021231384A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090207650A1 (en) * 2008-02-18 2009-08-20 Braceras George M System and method for integrating dynamic leakage reduction with write-assisted sram architecture
US20100208529A1 (en) * 2009-02-19 2010-08-19 Prashant Kenkare Memory with reduced power supply voltage for a write operation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090207650A1 (en) * 2008-02-18 2009-08-20 Braceras George M System and method for integrating dynamic leakage reduction with write-assisted sram architecture
US20100208529A1 (en) * 2009-02-19 2010-08-19 Prashant Kenkare Memory with reduced power supply voltage for a write operation

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