JP6470250B2 - 半導体チップのハウジングおよびハウジングを有する半導体チップ - Google Patents
半導体チップのハウジングおよびハウジングを有する半導体チップ Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 83
- 238000002347 injection Methods 0.000 claims description 58
- 239000007924 injection Substances 0.000 claims description 58
- 230000004308 accommodation Effects 0.000 claims description 33
- 239000012528 membrane Substances 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 7
- 238000009530 blood pressure measurement Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 239000012778 molding material Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000012530 fluid Substances 0.000 description 7
- 238000001746 injection moulding Methods 0.000 description 6
- 238000003466 welding Methods 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002925 chemical effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/092—Buried interconnects in the substrate or in the lid
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/094—Feed-through, via
- B81B2207/096—Feed-through, via through the substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Measuring Fluid Pressure (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Micromachines (AREA)
Description
好ましくは、このハウジングは半導体チップを損傷から保護し、たとえば外部からの機械的または化学的な作用から半導体チップを保護する。
さらに、本発明は、ハウジングを有する半導体チップに関する。
りわけ1つ以上のメタライジング部が、ハウジング壁に沿って延びていてよい。とりわけ1つ以上のメタライジング部が、ハウジング壁に沿って外部に導かれてよい。
2 半導体チップ
3 収容空間
4 射出成形体
5 半導体チップ固定用の接着剤
6 内側のメタライジング部
7 内側のメタライジング部
8 内側の表面
9 接続ワイヤ
10 接続ワイヤ
11 貫通接続部
12 貫通接続部
13 外面
14 外側のメタライジング部
15 外側のメタライジング部
16 内側の表面
17 バルク成形材
18 蓋
19 底部
20 接続パッド
21 接続パッド
22 導管部
23 空隙部
24 メタライジング部
25 メタライジング部
26 表面
27 蓋固定用の接着剤
28 受入部
29 接続ピン
30 接続ピン
31 開口部
Claims (19)
- 半導体チップのハウジングであって、
前記ハウジング(1)は、半導体チップ(2)を収容する収容空間(3)が設けられた射出成形体(4)を備え、
前記射出成形体(4)は、前記半導体チップ(2)と電気的に接続するための、少なくとも1つのメタライジング部(6,7,11,12,14,15,24,25)を備え、
前記ハウジング(1)は、それぞれ前記射出成形体(4)の一部から形成されている複数の接続ピンを備え、当該接続ピンの下面には前記メタライジング部(24,25)が配設されており、
前記接続ピン(29,30)は、前記接続ピン(29,30)の上面から見て、前記射出成形体の前記接続ピン以外の部分から横方向かつ下向きに突出している、
ことを特徴とする半導体チップのハウジング。 - 請求項1に記載のハウジングにおいて、
複数の前記接続ピン(29,30)が隣り合って配設されていることを特徴とするハウジング。 - 請求項1または2に記載のハウジングにおいて、
前記メタライジング部(24,25)と共に前記接続ピン(29,30)を形成する前記射出成形体(4)の前記一部は、前記メタライジング部(24,25)が配設されている底面を有し、
前記底面は、前記射出成形体(4)の他の部分よりも低い位置に配置されることを特徴とするハウジング。 - 請求項1乃至3のいずれか1項に記載のハウジングにおいて、
前記収容空間(3)の封止のための蓋(18)を備えることを特徴とするハウジング。 - 前記蓋(18)および前記接続ピン(29,30)は、前記ハウジング(1)の同じ側に配設されていることを特徴とする、請求項4に記載のハウジング。
- 前記接続ピン(29,30)は、前記蓋(18)から下側に突出していることを特徴とする、請求項5に記載のハウジング。
- 請求項1乃至6のいずれか1項に記載のハウジングにおいて、
前記メタライジング部(6,7,11,12,14,15,24,25)は、少なくとも部分的に前記射出成形体の表面(8,16,26)の上に配設されていることを特徴とするハウジング。 - 請求項1乃至7のいずれか1項に記載のハウジングにおいて、
前記メタライジング部(6,7,11,12,14,15,24,25)は、少なくとも部分的に前記収容空間(3)に配設されていることを特徴とするハウジング。 - 請求項1乃至8のいずれか1項に記載のハウジングにおいて、
前記メタライジング部(6,7,11,12,14,15,24,25)は、少なくとも部分的に前記射出成形体(4)を貫通していることを特徴とするハウジング。 - 請求項1乃至9のいずれか1項に記載のハウジングにおいて、
前記メタライジング部(6,7,11,12,14,15,24,25)は、少なくとも部分的に前記収容空間(3)の外側に配設されていることを特徴とするハウジング。 - 請求項1乃至10のいずれか1項に記載のハウジングにおいて、
前記射出成形体(4)は、前記収容空間(3)に配設された少なくとも1つのメタライジング部(6,7)を備え、前記射出成形体(4)を貫通する少なくとも1つの貫通接続部として形成されたメタライジング部(11,12)を備え、前記収容空間(3)の外側に配設された少なくとも1つのメタライジング部(14,15)を備え、
前記貫通接続部(11,12)は、前記収容空間(3)において、前記メタライジング部(6,7)を前記メタライジング部(24,25)と前記収容空間(3)の外側で電気的に接続していることを特徴とするハウジング。 - 請求項1乃至11のいずれか1項に記載のハウジングにおいて、
前記メタライジング部(24,25)は、少なくとも部分的に前記収容空間(3)に設けられ、前記射出成形体の表面(26)に沿って前記収容空間(3)から導出されていることを特徴とするハウジング。 - 請求項1乃至12のいずれか1項に記載のハウジングにおいて、
前記ハウジングは、前記収容空間(3)をハーメチックシール封止するように形成されていることを特徴とするハウジング。 - 請求項1乃至13のいずれか1項に記載のハウジングにおいて、
前記収容空間に通ずる開口部(31)を備えることを特徴とするハウジング。 - 請求項14に記載のハウジングにおいて、前記開口部(31)は、膜またはバルブにより封止されていることを特徴とするハウジング。
- 請求項14または15に記載のハウジングにおいて、
少なくとも1つの前記メタライジング部(6,7,11,12,14,15,24,25)が、前記収容空間から導出され、前記開口部(31)は、前記収容空間(3)で前記ハウジングの1つの側に延び、少なくとも1つの前記メタライジング部(6,7,11,12,14,15,24,25)は、前記収容空間(3)からもう1つの側に導出されていることを特徴とするハウジング。 - 請求項16に記載のハウジングにおいて、前記収容空間(3)を封止するための蓋(18)を備え、前記開口部(31)は前記蓋(18)に配設され、少なくとも1つの前記メタライジング部(6,7,11,12,14,15,24,25)は、ハウジング底部(19)に配設されているか、または、前記開口部はハウジング底部(19)に配設され、少なくとも1つの前記メタライジング部(6,7,11,12,14,15,24,25)は、前記蓋(18)が配設された側に配設されていることを特徴とするハウジング。
- 請求項1乃至17のいずれか1項に記載のハウジングを備えた半導体チップであって、
前記半導体チップ(2)は前記ハウジング(1)の前記収容空間(3)に配設されていることを特徴とする半導体チップ。 - 請求項18に記載の半導体チップにおいて、
前記半導体チップは、圧力測定用に作製されていることを特徴とする半導体チップ。
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DE102011109006A DE102011109006A1 (de) | 2011-07-29 | 2011-07-29 | Gehäuse für einen Halbleiterchip und Halbleiterchip mit einem Gehäuse |
DE102011109006.5 | 2011-07-29 |
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JP2014520692A Division JP2014522102A (ja) | 2011-07-29 | 2012-07-26 | 半導体チップのハウジングおよびハウジングを有する半導体チップ |
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JP2016251263A Active JP6470250B2 (ja) | 2011-07-29 | 2016-12-26 | 半導体チップのハウジングおよびハウジングを有する半導体チップ |
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US (1) | US9177880B2 (ja) |
EP (1) | EP2736836B1 (ja) |
JP (2) | JP2014522102A (ja) |
DE (1) | DE102011109006A1 (ja) |
WO (1) | WO2013017530A1 (ja) |
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US20140377915A1 (en) * | 2013-06-20 | 2014-12-25 | Infineon Technologies Ag | Pre-mold for a magnet semiconductor assembly group and method of producing the same |
US20150342069A1 (en) * | 2014-05-20 | 2015-11-26 | Freescale Semiconductor, Inc. | Housing for electronic devices |
JP6950796B2 (ja) * | 2017-10-05 | 2021-10-13 | カシオ計算機株式会社 | 電池モジュールの製造方法 |
CN112687631B (zh) * | 2020-12-25 | 2024-04-26 | 杭州耀芯科技有限公司 | 一种sip封装的装置及制备方法 |
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US5596231A (en) * | 1991-08-05 | 1997-01-21 | Asat, Limited | High power dissipation plastic encapsulated package for integrated circuit die |
ES2148564T3 (es) * | 1994-09-23 | 2000-10-16 | Siemens Nv | Bloque de matriz con proyecciones de polimero. |
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-
2011
- 2011-07-29 DE DE102011109006A patent/DE102011109006A1/de not_active Withdrawn
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2012
- 2012-07-26 JP JP2014520692A patent/JP2014522102A/ja active Pending
- 2012-07-26 US US14/127,451 patent/US9177880B2/en active Active
- 2012-07-26 WO PCT/EP2012/064724 patent/WO2013017530A1/de active Application Filing
- 2012-07-26 EP EP12740157.8A patent/EP2736836B1/de active Active
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Publication number | Publication date |
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EP2736836B1 (de) | 2023-01-18 |
DE102011109006A1 (de) | 2013-01-31 |
EP2736836A1 (de) | 2014-06-04 |
JP2017103464A (ja) | 2017-06-08 |
US9177880B2 (en) | 2015-11-03 |
JP2014522102A (ja) | 2014-08-28 |
WO2013017530A1 (de) | 2013-02-07 |
US20140217523A1 (en) | 2014-08-07 |
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