CN103489833A - 用于芯片的芯片封装模块和用于形成芯片封装模块的方法 - Google Patents
用于芯片的芯片封装模块和用于形成芯片封装模块的方法 Download PDFInfo
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Abstract
提供了一种用于芯片的芯片封装模块,所述芯片封装模块包括:包括第一芯片面的芯片,其中,所述第一芯片面包括配置成接收信号的输入部;配置成与所述第一芯片面电连接的芯片载体,其中,所述芯片经由所述第一芯片面安装到所述芯片载体;以及配置成在至少所述第一芯片面上覆盖所述芯片的成型材料,其中所述输入部的至少一部分被从所述成型材料解除。
Description
技术领域
本发明通常涉及一种芯片封装模块和一种用于形成芯片封装模块的方法。
背景技术
若干处理挑战围绕用于容纳芯片的芯片封装模块的生产。在芯片封装制造中,芯片常常被保护芯片的成型材料(mold material)覆盖。一些芯片特别地可以要求芯片的一部分被留下不被覆盖,例如,具有传感器的芯片。在这种情况下,当尝试留下芯片的一部分不被覆盖时,需要注意确保模具工具不碰撞或者破坏芯片。图1A示出了预成型的腔封装100,其中由成型材料140、140a形成的预成型的腔可以被用来容纳芯片102。在芯片102被插入到腔之前引线框架106可以形成腔封装的一部分。芯片102可以在芯片102的底面被粘合到引线框架106。芯片102的顶面可以具有电接触108,所述电接触108可以经由连接112(例如导电引线)连接到引线框架106。芯片102之上的软凝胶114的铸造是必需的步骤,其产生有关性能、可靠性和有关软凝胶114中的气泡的产生的问题。
图1B示出了其中芯片102可以使用芯片102之上的成型材料104a密封的腔封装110,其中成型材料104a可以通过成型工具的使用与芯片102连接,例如与芯片顶面连接。芯片102可以在芯片102的底面被粘合到引线框架106。复杂成型处理冒着损坏芯片102(例如芯片管芯)的风险,因为成型工具需要直接地在芯片102上密封。
图1C和1D分别示出了腔封装120和130,其中在图1C中软聚合物滴114可以被沉积在芯片102上,而在图1D中软聚合物铸件114a可以被沉积在芯片102上,例如在芯片102的顶面上的表面之上。芯片102可以在芯片102的底面被粘合到引线框架106。芯片102可以使用与芯片102连接(例如与芯片顶面连接)的成型材料104a和图1C中软聚合物滴114以及图1D中的软聚合物铸件114a密封。例如,成型材料104可以从底面覆盖芯片102,并且成型材料104a可以从顶面覆盖芯片102。在制造图1C的腔封装中,芯片102可以使用软聚合物滴114上的成型工具来密封。在制造图1D的腔封装中,芯片102可以使用软聚合物铸件114a上的成型工具来密封。复杂的成型处理冒着污染模具工具的风险。方法进一步需要引起制造重复能力的困难的复杂凝胶铸造处理。即使可以在传感器表面上使用上述方法,他们也被限于用在能够容许凝胶覆盖的表面上,其可能不包括多数的电、机械以及机电传感器。另外,因为凝胶铸造是必需的步骤,所以这可能影响芯片的性能。
发明内容
各种实施例提供了用于芯片的芯片封装模块,所述芯片封装模块包括:包括第一芯片面的芯片,其中所述第一芯片面包括配置成接收信号的输入部;配置成与所述第一芯片面电连接的芯片载体,其中所述芯片经由所述第一芯片面安装到所述芯片载体;以及配置成在至少所述第一芯片面覆盖所述芯片的成型材料,其中所述输入部的至少一部分被从所述成型材料解除。
附图说明
在图中,遍及不同视图相同的参考符号通常指代相同的部分。图未必按比例绘制,相反地重点通常被放在图示本发明的原理上。在以下描述中,参考以下各图对本发明的各种实施例进行了描述,其中:
图1A至1D示出了腔芯片封装;
图2示出了根据各种实施例的用于形成芯片封装模块的方法;以及
图3A至3G示出了根据各种实施例的用于形成如图3E、3F以及3G中所示出的芯片封装模块的方法。
具体实施方式
以下的具体描述涉及附图,其通过例图示出了其中可以实现本发明的特定细节和实施例。
单词“示例性的”在本文中被用来意指“充当示例、实例或例图”。在本文中描述为“示例性的”的任何实施例或设计不必被解释为对其它实施例或设计是优选的或有利的。
关于“在”面或表面“之上”形成的沉积材料所使用单词“在…之上”在本文中可以被用来意指所沉积的材料可以“直接在”所暗示的面或表面“上”( 例如与所暗示的面或表面直接接触)形成。关于“在”面或表面“之上”形成的沉积材料所使用单词“在…之上”在本文中可以被用来意指所沉积的材料可以“间接地在”所暗示的面或表面“上”形成,一个或多个额外的层布置在所暗示的面或表面与所沉积的材料之间。
各种实施例涉及用于电子部件的小成型的壳体的概念。
图2示出了根据一个实施例的用于形成芯片封装模块的方法200;该方法包括
形成与第一芯片面电连接的芯片载体,第一芯片面包括用于接收信号的输入部,并且经由第一芯片面将芯片安装到芯片载体 (在210中);以及
在至少第一芯片面上使用成型材料来覆盖芯片,其中输入部的至少一部分被从成型材料解除(release)(在220中)。
图3A至3G示出了根据图2用于形成芯片封装模块的方法的例图。图3E、3F以及3G示出了根据各种实施例的芯片封装模块。
在图3A中,如例图300中所示出的那样,芯片202包括第一芯片面222。芯片202(例如传感器芯片)可以包括在第一芯片面222(例如其有源面)上形成的输入部224,例如传感器区域224。输入部224可以包括膜片(membrane)。膜片可以被配置成包括机电结构,例如MEMS结构。一个或多个连接垫232(例如电接触)可以被形成在第一芯片面222(例如其有源面)上。一个或多个连接垫232可以被形成在和输入部224相同的面上。芯片202可以包括传感器,例如MEMS传感器、压力传感器、气体传感器,其中输入部224可以包括用于接收要由芯片202处理的信号的感测区域。芯片202可以包括通用传感器,其中可以提供到例如第一芯片面222上的有源芯片表面的开放通道(open access)。在某些情况下信号入口(inlet)可以被提供用于接收输入信号,在该情况下可以在感测期间提供与化学物质的直接接触。换句话说,与图1C和1D的腔封装相反,软聚合物滴114和软聚合物铸件114a中的任何一个在这样的实施例中可能不适合于覆盖第一芯片面222。芯片可以包括MEMS传感器,其中被至少部分地暴露于环境的第一芯片面222上的芯片表面是必需的。这样的传感器的示例包括致动器、泵以及其它移动结构(例如MEMS结构),其不被密封或喷涂。在各种实施例中,到芯片202的通道提供通过用于芯片的壳体到芯片的通道。芯片202可以包括半导体材料中的至少一种,例如硅。芯片202可以包括以下组的材料中的至少一种,该组包括塑料、玻璃以及聚合物。
如图3B的例图310中所示出的那样,层242(例如缓冲层)可以被沉积在第一芯片面222上。缓冲层242可以被选择性施加或结构化,例如选择性地定位和成形在第一芯片面222之上。缓冲层242可以包括来自以下组的材料中的至少一种,该组包括:粘合胶、环氧树脂、焊料、双面胶带、弹性聚合物、抗蚀剂、聚酰亚胺、在热处理之后充当粘合剂的透辉岩材料以及热粘合剂。缓冲层242可以被进一步配置成将输入部224与在第一芯片面222上形成的一个或多个连接垫232隔离。缓冲层242可以厚于连接垫232。缓冲层242可以通过旋涂(spin-coating)和印刷中的至少一种来沉积。缓冲层242可以通过箔(例如kaptop箔)的预施加(pre-application)来形成。缓冲层242可以具有从约5μm至约200μm范围的厚度,例如约10μm至约100μm,例如约20μm至约50μm。旋涂可以产生具有在约5μm至约10μm之间的厚度的缓冲层242的沉积。印刷可以产生具有在约50μm至约200μm之间的厚度的缓冲层242的沉积。箔的预施加可以产生具有在约50μm至约150μm之间的厚度的缓冲层242的沉积。
如图3C的例图320中所示出的那样,芯片202可以被附着到芯片载体226。芯片202可以被经由第一芯片面222安装到芯片载体226。芯片载体226可以被形成在第一芯片面222上。换句话说,芯片载体226可以被定位在第一芯片面222上。芯片载体226可以包括粘合到第一芯片面222的一部分的芯片载体面234。缓冲层242可以被配置成将芯片载体面234的至少一部分粘合到第一芯片面222的至少一部分。缓冲层242可以被进一步配置成将芯片202粘合到芯片载体226,而芯片载体226不与芯片202直接接触。缓冲层242可以位于第一芯片面222与芯片载体226之间。第一芯片面222可以使用粘合缓冲层242粘合(例如通过胶接合、焊接)到芯片载体226(例如引线框架)。可以布置芯片222使得第一芯片面222面向下并且被粘合到芯片载体226。
在芯片载体226中产生开口252(例如孔)的处理期间,输入部224可以被暴露,例如可以看得见,例如能够受环境的影响。通过在芯片载体226中产生相应的开口254(例如孔),连接垫232(例如电接触,例如引线结合垫)可以被暴露,例如暴露于环境。
芯片载体226可以被配置成与第一芯片面222电连接,其中至少一个引线238可以被配置成提供第一芯片面222与芯片载体226之间(例如在第一芯片面222上形成的一个或多个连接垫232中的至少一个与芯片载体226之间)的电连接。至少一个引线238可以被配置成馈送根据由输入部224所接收的信号由芯片处理得到的信号到芯片载体226。可以通过使用粘合剂258(例如胶、焊料材料)将至少一个引线238粘合到一个或多个连接垫232。芯片载体226可以包括配置成与第一芯片面222电连接的另外的芯片载体面236,例如,引线238可以被配置成提供第一芯片面222与另外的芯片载体面236之间(例如在第一芯片面232上形成的一个或多个连接垫232中的至少一个与另外的芯片载体面236之间)的电连接。
如图3D的例图330中所示出的那样,可以执行外模(overmold)处理使得可以随后执行密封成型处理(例如注入成型),紧跟着使用标准处理(例如隔离、测试、包装)进行封装。可以在修剪和形状(trim and form)处理之前执行外模处理。
优点是在外模处理期间,不是被直接地放置在芯片202上,模具工具256可以被放置在芯片载体226上,避免对芯片202造成损坏。注入工具放置在芯片载体226上相对地不要紧。在注入处理期间注入工具必须被干净地密封。
如图3E的例图340中所示出的那样,可以执行可以包括到模具工具256中的成型材料228的注入成型的密封处理。成型材料228可以被配置成在至少第一芯片面222上覆盖芯片200,其中输入部224的至少一部分被从成型材料228解除。换句话说,输入部224的至少一部分可以不被成型材料228覆盖。换句话说,输入部224的至少一部分可以具有开放通道以接收外部信号。外部信号可以是未从芯片内中继的信号。外部信号可以包括来自以下组的信号中的至少一种,所述组包括:运动信号、机械信号、电信号、化学信号、压力信号以及气态信号。成型材料228可以被配置成覆盖芯片载体226的至少一部分(例如另外的芯片载体面236)、引线238以及可以在第一芯片面222上形成的一个或多个连接垫232。成型材料228可以包括选自包括以下的组中的材料:填充或未填充的环氧树脂、预浸渍的合成纤维、层压物、热固性和热塑性材料。
成型材料228可以被进一步配置成在至少第二芯片面244上覆盖芯片202,其中第二芯片面244面向与第一芯片面222相反的方向,并且进一步配置成覆盖芯片载体面234的至少一部分。如果第一芯片面222面向第一方向246,则第二芯片面244面向相反的第二方向248。
可以在芯片202到芯片载体226的粘合之后执行外模和成型注入处理。紧跟着外模和成型处理可以在芯片载体226上执行修剪和形状处理。
根据如图3F的例图350中所示出的可替换的实施例,340中图示的布置可以被定位,例如旋转变化的量,例如旋转180。,使得连接引线238(例如连接结合引线)可以被牵引,从而提供可替换的修剪和形状选项。
根据如图3G的例图360中所示出的可替换的实施例,成型材料228可以被形成在缓冲层242的至少一部分之上以及在引线框架226上,例如直接在缓冲层242的至少一部分上。因此,诸如缓冲层242a等缓冲层242的特定部分不必被引线框架226覆盖。
芯片202可以包括来自以下组的传感器中的至少一种,所述组包括:电传感器、机械传感器、机电传感器、微机电传感器、压力传感器、气体传感器、化学传感器、生物传感器、泵以及致动器。输入部224可以包括配置成接收外部信号的感测表面。输入部224可以包括可以用于压力感测和声学传感器(例如麦克风)的膜片;用于气体感测的金属氧化物,例如在暴露于气体之后可以改变它们的电阻的金属氧化物;DNA斑块(DNA-spot),其当与外部物质接触时显示感测反应。输入部224可以包括晶体管栅极,例如CMOS晶体管栅极,其可以在与外部物质相互作用后改变晶体管增益。输入部224可以包括可以被配置为传感器的硅、多晶硅、单晶硅中的至少一种。输入部224可以进一步包括保护层(例如钝化层)、氧化物、氮化物、酰亚胺,只要它不破坏传感器功能或者限制输入部224感测外部信号的能力。输入部224可以包括膜片,并且可以被配置成接收来自以下组的信号中的至少一种:运动、机械、电、化学、压力以及气态。芯片202可以包括芯片实验室(lab-on-chip)(芯片上的实验室(laboratory- on-chip))。芯片实验室可以包括在芯片上包括传感器的芯片,其中传感器可以被配置成处理实验室测试。例如,输入部224可以包括用于接收信号的感测表面,例如来自生物分子、细胞、液体、化学测定、免疫测定的信号,并且芯片202可以包括用于处理所接收的信号的电路。
芯片载体226可以包括引线框架和层压物(例如陶瓷层压物和有机层压物)中的至少一个。芯片载体226可以优选地为金属物质,并且可以包括以下中的至少一种:有机材料、陶瓷材料、单层或多层基底。
根据一个实施例,可以进行芯片载体226上一个或多个芯片202的轻柔小心的装配的引入。例如,可以通过缓冲层242(例如机械应力缓冲器,例如密封环,例如在芯片202上沉积的密封结构材料)的引入来执行轻柔小心的装配。优选的变体为,通过其可以已经在芯片载体226上施加粘合剂,例如胶,例如类似于双面粘合胶带的胶。
缓冲层242可以被配置成具有降低由模具工具造成的损坏的风险的厚度和软度。实施例有利地提供用于芯片202必须低应力装配的应用。第二芯片面244可以使用凝胶覆盖,尽管凝胶密封在原理上不是必须的。实施例提供了面朝下芯片装配的可能性,从而不必使用昂贵的倒装芯片处理,例如凸块制造处理。可以改为使用较便宜的引线结合处理。成型第二芯片面244是必不可少的。基于这样的芯片202抵抗机械应力的分布广的应力灵敏性,实施例特别通过厚弹性胶的使用提供了用于芯片壳体的无应力实施例。这在芯片实验室技术中产生了不太昂贵的MEMS传感器壳体。
例图340和350示出了根据各种实施例的用于芯片202的芯片封装模块200。遍及包括例图340和350的芯片封装模块200以及例图360的芯片封装模块210的、将在下文更详细地描述的所有实施例,参考图2和图3A至3G所描述的特征的基本功能都将被涉及并且是适用的。完全相同的特征使用相同的参考符号来表示。
根据一个实施例,用于芯片202的芯片封装模块200可以包括包括第一芯片面222的芯片202,其中第一芯片面222包括配置成接收信号的输入部224。芯片202可以包括用于处理所接收的信号的电路。芯片载体226可以被配置成与第一芯片面222电连接,其中芯片202可以经由第一芯片面222安装到芯片载体226。芯片封装模块200可以进一步包括配置成在至少第一芯片面222上覆盖芯片200的成型材料228,其中输入部224的至少一部分可以从成型材料228解除。
根据一个实施例,一个或多个连接垫232可以被形成在第一芯片面222上。
根据一个实施例,芯片载体226可以被配置成与在第一芯片面222上形成的一个或多个连接垫232中的至少一个电连接。
根据一个实施例,芯片202可以包括来自以下组的传感器中的至少一种,所述组包括:电传感器、机械传感器、机电传感器、微机电传感器、压力传感器、气体传感器、化学传感器、生物传感器、泵以及致动器。
根据一个实施例,输入部224可以包括膜片。
根据一个实施例,输入部224可以被配置成接收来自以下组的信号中的至少一种,所述组包括:运动信号、机械信号、电信号、化学信号、压力信号以及气态信号。
根据一个实施例,芯片202可以包括芯片实验室(lab-on-chip)。
根据一个实施例,芯片载体226可以包括粘合到第一芯片面222的一部分的芯片载体面234。
根据一个实施例,芯片载体226可以包括配置成与第一芯片面222电连接的另外的芯片载体面236。
根据一个实施例,芯片载体226可以进一步包括配置成提供第一芯片面222与芯片载体226之间的电连接的至少一个引线238。
根据一个实施例,芯片封装模块200可以进一步包括在第一芯片面222上形成的缓冲层242,其中缓冲层242位于芯片202与芯片载体226之间。
根据一个实施例,缓冲层242可以被配置成将芯片载体面234的至少一部分粘合到第一芯片面222的至少一部分。
根据一个实施例,缓冲层242可以包括来自以下组的材料中的至少一种,所述组包括:粘合胶、环氧树脂、焊料、双面胶带、弹性聚合物、抗蚀剂、聚酰亚胺、透辉岩材料以及热粘合剂。
根据一个实施例,缓冲层242可以被配置成将输入部224与在第一芯片面222上形成的连接垫232隔离。
根据一个实施例,成型材料228可以包括来自以下组的材料中的至少一种,所述组包括:填充或未填充的环氧树脂、预浸渍的合成纤维、层压物、热固性和热塑性材料。在可替换的实施例中可以使用任何其它适合的成型材料。
根据一个实施例,成型材料228可以被进一步配置成覆盖芯片载体226的至少一部分。
根据一个实施例,成型材料228可以被进一步配置成在第二芯片面244的至少一部分上覆盖芯片202,其中第二芯片面244面向与第一芯片面222相反的方向。
根据一个实施例,成型材料228可以被形成在缓冲层242的至少一部分之上。
根据一个实施例,芯片载体226可以包括引线框架和层压物中的至少一个。
例图360示出了根据一个实施例的用于芯片202的芯片封装模块210。芯片封装模块210具有芯片封装模块200的所有特征。芯片封装模块210进一步包括成型材料228,所述成型材料228可以被形成在缓冲层242的至少一部分以及引线框架226的一部分之上,例如直接形成在缓冲层242的至少一部分以及引线框架226的一部分上。因此,诸如缓冲层242a的缓冲层242的特定部分不必被引线框架226覆盖。
虽然已经参考特定实施例具体地示出并且描述了本发明,但是本领域的技术人员应该理解的是,在不背离如由随附权利要求限定的本发明的精神和范围的情况下,可以在其中进行形式和细节上的各种变化。本发明的范围因此由随附权利要求来指示,并且因此旨在包括落入权利要求的等同物的意义和范围内的所有变化。
Claims (20)
1.一种用于芯片的芯片封装模块,所述芯片封装模块包括:
包括第一芯片面的芯片,其中,所述第一芯片面包括配置成接收信号的输入部;
配置成与所述第一芯片面电连接的芯片载体,并且其中,所述芯片经由所述第一芯片面安装到所述芯片载体;以及
配置成在至少所述第一芯片面上覆盖所述芯片的成型材料,其中,所述输入部的至少一部分被从所述成型材料解除。
2.根据权利要求1所述的芯片封装模块,其中,一个或多个连接垫被形成在所述第一芯片面上。
3.根据权利要求1所述的芯片封装模块,其中,所述芯片载体被配置成与在所述第一芯片面上形成的一个或多个连接垫中的至少一个电连接。
4.根据权利要求1所述的芯片封装模块,其中,所述芯片包括来自以下组的传感器中的至少一种,所述组包括:电传感器、机械传感器、机电传感器、微机电传感器、压力传感器、气体传感器、化学传感器、生物传感器、泵以及致动器。
5.根据权利要求1所述的芯片封装模块,其中,所述输入部包括膜片。
6.根据权利要求1所述的芯片封装模块,其中,所述输入部被配置成接收来自以下组的信号中的至少一种,所述组包括:运动信号、机械信号、电信号、化学信号、压力信号以及气态信号。
7.根据权利要求1所述的芯片封装模块,其中,所述芯片包括芯片实验室。
8.根据权利要求1所述的芯片封装模块,其中,所述芯片载体包括粘合到所述第一芯片面的一部分的芯片载体面。
9.根据权利要求1所述的芯片封装模块,其中,所述芯片载体包括配置成与所述第一芯片面电连接的另外的芯片载体面。
10.根据权利要求1所述的芯片封装模块,其中,所述芯片载体进一步包括配置成提供所述第一芯片面与所述芯片载体之间的所述电连接的至少一个引线。
11.根据权利要求1所述的芯片封装模块,进一步包括在所述第一芯片面上形成的缓冲层,其中,所述缓冲层位于所述芯片与所述芯片载体之间。
12.根据权利要求11所述的芯片封装模块,其中,所述缓冲层被配置成将所述芯片载体的至少一部分粘合到所述第一芯片面的至少一部分。
13.根据权利要求11所述的芯片封装模块,其中,所述缓冲层可以包括来自以下组的材料中的至少一种,所述组包括:粘合胶、环氧树脂、焊料、双面胶带、弹性聚合物、抗蚀剂、聚酰亚胺、透辉岩材料以及热粘合剂。
14.根据权利要求11所述的芯片封装模块,其中,所述缓冲层可以被配置成将所述输入部与在所述第一芯片面上形成的连接垫隔离。
15.根据权利要求1所述的芯片封装模块,其中,所述成型材料包括选自包括以下组的材料:填充或未填充的环氧树脂、预浸渍的合成纤维、层压物、热固性和热塑性材料。
16.根据权利要求1所述的芯片封装模块,其中,所述成型材料被进一步配置成覆盖所述芯片载体的至少一部分。
17.根据权利要求1所述的芯片封装模块,其中,所述成型材料被进一步配置成在第二芯片面的至少一部分上覆盖所述芯片,其中所述第二芯片面面向与所述第一芯片面相反的方向。
18.根据权利要求11所述的芯片封装模块,其中,所述成型材料被形成在所述缓冲层的至少一部分之上。
19.根据权利要求1所述的芯片封装模块,其中,所述芯片载体包括引线框架和层压物中的至少一个。
20.一种用于形成芯片封装模块的方法,包括:
形成与第一芯片面电连接的芯片载体,所述第一芯片面包括用于接收信号的输入部,并且经由所述第一芯片面将所述芯片安装到所述芯片载体;以及
在至少所述第一芯片面上使用成型材料来覆盖所述芯片,其中,所述输入部的至少一部分被从所述成型材料解除。
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