JP6448189B2 - 映像処理装置 - Google Patents

映像処理装置 Download PDF

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Publication number
JP6448189B2
JP6448189B2 JP2013271794A JP2013271794A JP6448189B2 JP 6448189 B2 JP6448189 B2 JP 6448189B2 JP 2013271794 A JP2013271794 A JP 2013271794A JP 2013271794 A JP2013271794 A JP 2013271794A JP 6448189 B2 JP6448189 B2 JP 6448189B2
Authority
JP
Japan
Prior art keywords
video signal
video
video signals
input
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013271794A
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English (en)
Japanese (ja)
Other versions
JP2015125411A5 (enExample
JP2015125411A (ja
Inventor
敦史 石井
敦史 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2013271794A priority Critical patent/JP6448189B2/ja
Priority to US14/566,876 priority patent/US10212316B2/en
Publication of JP2015125411A publication Critical patent/JP2015125411A/ja
Publication of JP2015125411A5 publication Critical patent/JP2015125411A5/ja
Application granted granted Critical
Publication of JP6448189B2 publication Critical patent/JP6448189B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
JP2013271794A 2013-12-27 2013-12-27 映像処理装置 Expired - Fee Related JP6448189B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013271794A JP6448189B2 (ja) 2013-12-27 2013-12-27 映像処理装置
US14/566,876 US10212316B2 (en) 2013-12-27 2014-12-11 Video processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013271794A JP6448189B2 (ja) 2013-12-27 2013-12-27 映像処理装置

Publications (3)

Publication Number Publication Date
JP2015125411A JP2015125411A (ja) 2015-07-06
JP2015125411A5 JP2015125411A5 (enExample) 2017-02-09
JP6448189B2 true JP6448189B2 (ja) 2019-01-09

Family

ID=53483343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013271794A Expired - Fee Related JP6448189B2 (ja) 2013-12-27 2013-12-27 映像処理装置

Country Status (2)

Country Link
US (1) US10212316B2 (enExample)
JP (1) JP6448189B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10638082B2 (en) * 2014-08-28 2020-04-28 Gregory A. Pearson, Inc. Systems and methods for picture-in-picture video conference functionality
JP6307655B1 (ja) * 2017-10-23 2018-04-04 イメージニクス株式会社 映像信号処理装置
DE102021120037A1 (de) * 2020-08-21 2022-02-24 Panasonic Intellectual Property Management Co., Ltd. Videoverarbeitungsvorrichtung und Videoverarbeitungssystem
US12198657B2 (en) * 2021-01-22 2025-01-14 Sony Semiconductor Solutions Corporation Image processing device, image processing method, and image display device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2595551B2 (ja) * 1987-08-14 1997-04-02 ソニー株式会社 画像信号処理装置
JP3423327B2 (ja) 1991-09-19 2003-07-07 オリンパス光学工業株式会社 映像信号入出力装置
US5914757A (en) * 1997-04-21 1999-06-22 Philips Electronics North America Corporation Synchronization of multiple video and graphic sources with a display using a slow PLL approach
JP3919767B2 (ja) * 1999-01-29 2007-05-30 キヤノン株式会社 画像処理装置
US7106384B1 (en) 1999-02-09 2006-09-12 Micronas Gmbh Method and device for simultaneously representing at least a first and a second sequence of pictures in an overall picture
JP4047316B2 (ja) * 2003-09-25 2008-02-13 キヤノン株式会社 フレームレート変換装置、それに用いられる追い越し予測方法、表示制御装置及び映像受信表示装置
JP2006267663A (ja) * 2005-03-24 2006-10-05 Canon Inc タイミング制御装置及び信号処理装置
JP2007271848A (ja) 2006-03-31 2007-10-18 Casio Comput Co Ltd 映像出力装置、及び映像出力方法
JP2010119026A (ja) * 2008-11-14 2010-05-27 Panasonic Corp 画像表示装置および画像表示装置の垂直同期制御方法
JP5488624B2 (ja) * 2012-02-03 2014-05-14 カシオ計算機株式会社 映像出力装置、及び映像出力方法

Also Published As

Publication number Publication date
US20150189127A1 (en) 2015-07-02
JP2015125411A (ja) 2015-07-06
US10212316B2 (en) 2019-02-19

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