JP6419785B2 - Icチップを基板に搭載させるための基板上のパッド・アレイ構造、並びに当該パッド・アレイ構造を有する光モジュール - Google Patents
Icチップを基板に搭載させるための基板上のパッド・アレイ構造、並びに当該パッド・アレイ構造を有する光モジュール Download PDFInfo
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- JP6419785B2 JP6419785B2 JP2016510274A JP2016510274A JP6419785B2 JP 6419785 B2 JP6419785 B2 JP 6419785B2 JP 2016510274 A JP2016510274 A JP 2016510274A JP 2016510274 A JP2016510274 A JP 2016510274A JP 6419785 B2 JP6419785 B2 JP 6419785B2
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- Prior art keywords
- pad
- row
- pad array
- pads
- signal
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10121—Optical component, e.g. opto-electronic component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Semiconductor Integrated Circuits (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
100 光電気混載基板
11,22,22’ 「S」列
22a,22b,22b’ 差動信号パッドの対
221〜224,223’ 信号パッド
12,14,21,21’,24 「G」列
211〜213,212’ グランド・パッド
13,23 「V」列
15,25 信号配線
16 グランド配線
26,27 IC電源パッド配置列
28,29 IC制御パッド配置領域
30 ICグランド配線
50,50’ 差動信号パッド
51,51’ グランド・パッド
501,501’ 信号配線
502〜504,502’ グランド配線
505,505’ 電源配線
52 IC制御パッド
200 シリコン・インターポーザ
210 CPUチップ
220 光学エンジン
Claims (6)
- ICチップを基板に搭載させるための該基板上のパッド・アレイ構造であって、パッド・アレイ領域の第1周縁部に、
第1列に等間隔に配列された複数のグランド・パッドと、
前記第1列の内側且つ第1列と平行の第2列に等間隔に配列された複数の信号パッドとを備え、
各前記信号パッドが、前記第1列において隣り合う2つの前記グランド・パッド間を通って前記基板上の外部回路に接続され、該外部回路との間で電気信号が入出力され、
前記複数の信号パッドが、複数の差動信号パッドの対を構成し、
前記第1周縁部の第1列における各前記グランド・パッドが、前記第1周縁部の第2列において隣り合う2つの前記差動信号パッド対の間の位置に対応する位置に配置される、パッド・アレイ構造。 - 請求項1記載のパッド・アレイ構造において、
前記第1周縁部の第1列における前記グランド・パッドの少なくとも1つが、前記第1周縁部の第2列において隣り合う前記2つの差動信号パッド対の中間に対応する位置に配置される、パッド・アレイ構造。 - 請求項1または2記載のパッド・アレイ構造において、更に、前記パッド・アレイ領域において第1周縁部に対向する第2周縁部の両端部分の内側近傍に複数のIC制御パッドを配置することを特徴とする、パッド・アレイ構造。
- 請求項1〜3のいずれか一項記載のパッド・アレイ構造を有する光モジュールであって、前記ICチップが、光電気混載基板上に搭載され、且つ光デバイスを駆動させるためのドライバIC、光信号を受信するためのレシーバIC、または光信号を送信するためのトランシーバICのいずれかであることを特徴とする、光モジュール。
- 請求項4記載の光モジュールであって、更に、前記パッド・アレイ領域において前記第1周縁部の第2列の内側に配列された第2の複数のグランド・パッドを備え、それぞれを、前記ICチップを介して前記第1周縁部の第1列におけるグランド・パッドに接続させることを特徴とする、光モジュール。
- 請求項1〜3のいずれか一項記載のパッド・アレイ構造を有するシリコン・インターポーザ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014059690 | 2014-03-24 | ||
JP2014059690 | 2014-03-24 | ||
PCT/JP2015/058012 WO2015146738A1 (ja) | 2014-03-24 | 2015-03-18 | Icチップを基板に搭載させるための基板上のパッド・アレイ構造、並びに当該パッド・アレイ構造を有する光モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2015146738A1 JPWO2015146738A1 (ja) | 2017-04-13 |
JP6419785B2 true JP6419785B2 (ja) | 2018-11-07 |
Family
ID=54195260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016510274A Expired - Fee Related JP6419785B2 (ja) | 2014-03-24 | 2015-03-18 | Icチップを基板に搭載させるための基板上のパッド・アレイ構造、並びに当該パッド・アレイ構造を有する光モジュール |
Country Status (5)
Country | Link |
---|---|
US (1) | US9775245B2 (ja) |
EP (1) | EP3125285B1 (ja) |
JP (1) | JP6419785B2 (ja) |
CN (1) | CN106104792B (ja) |
WO (1) | WO2015146738A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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US10231325B1 (en) * | 2016-12-20 | 2019-03-12 | Juniper Networks, Inc. | Placement of vias in printed circuit board circuits |
US10405425B2 (en) * | 2017-06-19 | 2019-09-03 | Dell Products, L.P. | Surface mount technology (SMT) pad design with differential contact strips having converging narrowing distal ends that facilitate high speed communication |
TWI622150B (zh) * | 2017-09-08 | 2018-04-21 | 瑞昱半導體股份有限公司 | 電子封裝構件以及電路佈局結構 |
CN107734828B (zh) * | 2017-09-14 | 2019-12-17 | 苏州浪潮智能科技有限公司 | 一种pcb板差分信号线布线结构及布线方法 |
US10314162B1 (en) * | 2018-07-13 | 2019-06-04 | Mellanox Technologies, Ltd. | Apparatuses and methods for improved network connections |
WO2020248125A1 (zh) * | 2019-06-11 | 2020-12-17 | 华为技术有限公司 | 电路板及电子设备 |
CN112566353A (zh) * | 2019-09-26 | 2021-03-26 | 中兴通讯股份有限公司 | 一种电路板及通信设备 |
CN112687653A (zh) * | 2020-12-01 | 2021-04-20 | 贵州振华风光半导体有限公司 | 一种用于集成电路封装的高速模数转换器有机基板 |
TWI769063B (zh) * | 2021-03-25 | 2022-06-21 | 嘉雨思科技股份有限公司 | 訊號傳輸電路封裝結構 |
CN113438800B (zh) * | 2021-06-29 | 2023-04-07 | 展讯通信(上海)有限公司 | 终端设备 |
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JP2000349192A (ja) * | 1999-06-07 | 2000-12-15 | Canon Inc | 半導体集積回路およびプリント配線板 |
US6249047B1 (en) * | 1999-09-02 | 2001-06-19 | Micron Technology, Inc. | Ball array layout |
US6384341B1 (en) | 2001-04-30 | 2002-05-07 | Tyco Electronics Corporation | Differential connector footprint for a multi-layer circuit board |
TW200408091A (en) * | 2001-11-13 | 2004-05-16 | Koninkl Philips Electronics Nv | Device for shielding transmission lines from ground or power supply |
US6885102B2 (en) * | 2002-08-26 | 2005-04-26 | Intel Corporation | Electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts |
US6908340B1 (en) * | 2003-09-11 | 2005-06-21 | Xilinx, Inc. | Method and system for reducing crosstalk in a backplane |
US7057115B2 (en) * | 2004-01-26 | 2006-06-06 | Litton Systems, Inc. | Multilayered circuit board for high-speed, differential signals |
JP2005340741A (ja) | 2004-05-31 | 2005-12-08 | Renesas Technology Corp | 半導体装置 |
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US8302067B2 (en) * | 2009-10-19 | 2012-10-30 | National Chiao Tung University | Pin-out designation method for package-board codesign |
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JP2011171415A (ja) * | 2010-02-17 | 2011-09-01 | Seiko Epson Corp | 半導体集積回路 |
US8860193B2 (en) * | 2010-06-04 | 2014-10-14 | Marvell World Trade Ltd. | Pad configurations for an electronic package assembly |
JP5654288B2 (ja) | 2010-08-24 | 2015-01-14 | 日本オクラロ株式会社 | 光モジュール及び高周波モジュール |
JP5352551B2 (ja) * | 2010-09-07 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2015
- 2015-03-18 US US15/128,904 patent/US9775245B2/en active Active
- 2015-03-18 EP EP15769376.3A patent/EP3125285B1/en active Active
- 2015-03-18 CN CN201580016004.1A patent/CN106104792B/zh not_active Expired - Fee Related
- 2015-03-18 JP JP2016510274A patent/JP6419785B2/ja not_active Expired - Fee Related
- 2015-03-18 WO PCT/JP2015/058012 patent/WO2015146738A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
EP3125285B1 (en) | 2019-09-18 |
EP3125285A4 (en) | 2017-11-29 |
US9775245B2 (en) | 2017-09-26 |
CN106104792B (zh) | 2018-09-18 |
US20170105284A1 (en) | 2017-04-13 |
WO2015146738A1 (ja) | 2015-10-01 |
CN106104792A (zh) | 2016-11-09 |
JPWO2015146738A1 (ja) | 2017-04-13 |
EP3125285A1 (en) | 2017-02-01 |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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LAPS | Cancellation because of no payment of annual fees |