JP6375517B2 - マイクロ波回路 - Google Patents
マイクロ波回路 Download PDFInfo
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- JP6375517B2 JP6375517B2 JP2015523841A JP2015523841A JP6375517B2 JP 6375517 B2 JP6375517 B2 JP 6375517B2 JP 2015523841 A JP2015523841 A JP 2015523841A JP 2015523841 A JP2015523841 A JP 2015523841A JP 6375517 B2 JP6375517 B2 JP 6375517B2
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- 239000000758 substrate Substances 0.000 claims description 259
- 230000005540 biological transmission Effects 0.000 claims description 16
- 239000011347 resin Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 11
- 230000008054 signal transmission Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 112
- 239000010410 layer Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Combinations Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
特許文献1の半導体装置において、複数の半田ボールが2枚の基板の端部に配置されることを想定する。この場合、スルーホールの径に比べて大きな径を有する半田ボールが、基板の外周に沿って複数並べられるので、パッケージ基板の面積が大きくなり、モジュールを小型化することが困難である。
図1(A)は、第1の実施形態におけるマイクロ波回路が搭載されたモジュールの構造例を示す平面図を示す。図1(A)は、上方(Z軸正方向)からモジュールを透視した場合の下基板5の面を示す。図1(B)は、モジュール1の構造例を示す断面図であり、図1(A)のA−A断面図である。図1(B)では、右端(X軸正方向の端部)の一部の図示を省略している。
第1の実施形態では、下基板に2個のLSIが実装される場合を示したが、第2の実施形態では、上基板と下基板にそれぞれLSIが実装される場合を示す。
第3の実施形態では、半田ボールの代わりに、ビアを用いて上基板と下基板とが接続される場合を示す。
本開示の第1のマイクロ波回路は、多層基板である第1基板と、第1基板と対向する第2基板と、第1基板の第1層と第2基板とを電気的に接続する複数の第1の導電性部材と、第1基板の第1層と第1基板の他層と、を電気的に接続し、第1の導電性部材の径よりも短い径を有する複数の第2の導電性部材と、第1の導電性部材と第2の導電性部材とを接続する伝送線路と、を備え、複数の第1の導電性部材及び複数の第2の導電性部材は、第1基板の端部に沿って、交互に配置されている。
3,3A,3B,3E,3G 上基板
5,5A,5B,5E,5G 下基板
5a 金属層
5b 誘電体層
5c GND層
6,6A,6B,6E,6G 樹脂モールド
7,7A,7B マイクロ波回路
8,8A,8B,9,9A,9B LSI
11,11A,11B,11C,11E,11G,19 半田ボール
12,12A,12B,12C,12E,12G,22,22A,22B,22C,22E,22G パッド
15,15A,15B,25,25A,25B,25C,25D 伝送線路
16,16A,16B,26,26A,26B,26C,26D 基板内ビア
17,17A,17B,18,27,27A,27B,27C,27D ビア用パッド
31,32 禁止エリア
51A,51B,51C,51D,51E,51G モールド貫通ビア
51g 孔
Claims (6)
- 多層基板である第1基板と、
前記第1基板と対向する第2基板と、
前記第1基板の第1層と前記第2基板とを電気的に接続する複数の第1の導電性部材と、
前記第1基板の前記第1層と前記第1基板の他層とを電気的に接続し、前記第1の導電性部材の径よりも短い径を有する複数の第2の導電性部材と、
前記第1の導電性部材と、前記複数の前記第2の導電性部材のうち前記第1の導電性部材に対応する前記第2の導電性部材とを接続する伝送線路と、
を備え、
前記第1の導電性部材及び前記複数の前記第2の導電性部材のうち前記第1の導電性部材に対応しない前記第2の導電性部材は、前記第1基板の端部に沿って、隣接して配置されている、
前記第1の導電性部材及び前記複数の第2の導電性部材は、導電性を有する貫通孔である、
マイクロ波回路。 - 前記複数の前記第1の導電性部材の一部は、前記第1基板の端部に沿って配置され、残りの第1の導電性部材は、前記複数の前記第1の導電性部材の一部よりも前記第1基板の中心部側に配置された、
請求項1に記載のマイクロ波回路。 - 前記第1の導電性部材は、導電性を有するボールであり、
前記第2の導電性部材は、導電性を有する貫通孔である、
請求項1または2に記載のマイクロ波回路。 - 前記第1基板と前記第2基板との間に樹脂が充填されたモールド部をさらに備える、
請求項1ないし3のいずれか1項に記載のマイクロ波回路。 - 前記第1基板の第1層と、前記第1基板と対向する第2基板又は前記第1基板の他層と、を電気的に接続する第3の導電性部材をさらに備え、
前記第1の導電性部材は、グランド用の導電性部材であり、
前記第3の導電性部材は、信号伝送用の導電性部材であり、
前記第1の導電性部材は、前記第3の導電性部材よりも前記第1基板の端部に近接して配置されている、
請求項1ないし4のいずれか1項に記載のマイクロ波回路。 - 前記第3の導電性部材は、前記第1基板の第1層と、前記第1基板と対向する第2基板と、を電気的に接続し、
前記第1基板に、第1の信号処理回路が実装され、
前記第2基板に、第2の信号処理回路が実装された、
請求項5に記載のマイクロ波回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013132928 | 2013-06-25 | ||
JP2013132928 | 2013-06-25 | ||
PCT/JP2014/002933 WO2014208010A1 (ja) | 2013-06-25 | 2014-06-03 | マイクロ波回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2014208010A1 JPWO2014208010A1 (ja) | 2017-02-23 |
JP6375517B2 true JP6375517B2 (ja) | 2018-08-22 |
Family
ID=52141386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015523841A Expired - Fee Related JP6375517B2 (ja) | 2013-06-25 | 2014-06-03 | マイクロ波回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9601818B2 (ja) |
JP (1) | JP6375517B2 (ja) |
WO (1) | WO2014208010A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20240096858A1 (en) * | 2022-09-15 | 2024-03-21 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6521845B1 (en) * | 1997-06-12 | 2003-02-18 | Intel Corporation | Thermal spreading enhancements for motherboards using PBGAs |
US5929729A (en) * | 1997-10-24 | 1999-07-27 | Com Dev Limited | Printed lumped element stripline circuit ground-signal-ground structure |
US6239385B1 (en) * | 1998-02-27 | 2001-05-29 | Agilent Technologies, Inc. | Surface mountable coaxial solder interconnect and method |
JP3725766B2 (ja) | 1999-07-19 | 2005-12-14 | 株式会社日立国際電気 | キャビティ付きスロットアレーアンテナ |
JP4623850B2 (ja) * | 2001-03-27 | 2011-02-02 | 京セラ株式会社 | 高周波半導体素子収納用パッケージおよびその実装構造 |
JP2004047702A (ja) * | 2002-07-11 | 2004-02-12 | Toshiba Corp | 半導体装置積層モジュール |
JP2007103681A (ja) * | 2005-10-05 | 2007-04-19 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4825529B2 (ja) | 2006-02-06 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4889359B2 (ja) * | 2006-04-14 | 2012-03-07 | ルネサスエレクトロニクス株式会社 | 電子装置 |
KR20090027325A (ko) * | 2007-09-12 | 2009-03-17 | 삼성전자주식회사 | 반도체 패키지 및 이를 갖는 반도체 모듈 |
JP4991637B2 (ja) * | 2008-06-12 | 2012-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2010153831A (ja) * | 2008-11-25 | 2010-07-08 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置、及び半導体素子 |
JP5107959B2 (ja) | 2009-04-09 | 2012-12-26 | ルネサスエレクトロニクス株式会社 | 基板 |
JP5143211B2 (ja) * | 2009-12-28 | 2013-02-13 | パナソニック株式会社 | 半導体モジュール |
US7915079B1 (en) * | 2010-02-04 | 2011-03-29 | Headway Technologies, Inc. | Method of manufacturing layered chip package |
KR101767108B1 (ko) * | 2010-12-15 | 2017-08-11 | 삼성전자주식회사 | 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법 |
JP2012204631A (ja) * | 2011-03-25 | 2012-10-22 | Fujitsu Semiconductor Ltd | 半導体装置、半導体装置の製造方法及び電子装置 |
US9842798B2 (en) * | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
JP5372235B2 (ja) | 2012-10-04 | 2013-12-18 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置実装体 |
-
2014
- 2014-06-03 JP JP2015523841A patent/JP6375517B2/ja not_active Expired - Fee Related
- 2014-06-03 US US14/420,265 patent/US9601818B2/en not_active Expired - Fee Related
- 2014-06-03 WO PCT/JP2014/002933 patent/WO2014208010A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US9601818B2 (en) | 2017-03-21 |
JPWO2014208010A1 (ja) | 2017-02-23 |
WO2014208010A1 (ja) | 2014-12-31 |
US20150207197A1 (en) | 2015-07-23 |
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