JP6341796B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6341796B2 JP6341796B2 JP2014160870A JP2014160870A JP6341796B2 JP 6341796 B2 JP6341796 B2 JP 6341796B2 JP 2014160870 A JP2014160870 A JP 2014160870A JP 2014160870 A JP2014160870 A JP 2014160870A JP 6341796 B2 JP6341796 B2 JP 6341796B2
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Description
以下、図面を参照しながら本実施の形態1の半導体装置の構造および製造工程について詳細に説明する。本実施の形態1では、半導体装置が、半導体基板の表面側から光を入射する表面照射型のCMOSイメージセンサである例について説明する。
図1は、本実施の形態1の半導体装置の構成例を示す回路ブロック図である。図2は、画素の構成例を示す回路図である。なお、図1では、アレイ状(行列状)に配置された4行4列(4×4)の16個の画素を示すが、画素の配列数はこれに限定されず、種々変更可能であり、例えば、実際にカメラなどの電子機器に使用される画素数は数百万のものがある。
次に、本実施の形態1の半導体装置の断面図(図5および図6)を参照しながら、本実施の形態1の半導体装置の構造を説明する。図5および図6は、本実施の形態1の半導体装置の断面図であり、図5は、図3のA−A線に沿った断面図にほぼ対応し、図6は、図4のB−B線での断面図にほぼ対応している。
次に、本実施の形態1の半導体装置の製造方法について、図5〜図24を参照して説明する。図面簡略化のために図23および図24に続く製造工程は、図5および図6を用いて説明する。
フォトダイオードPDの電荷蓄積層上の表面層を低濃度のサブ領域PR1と高濃度のサブ領域PR2とで構成し、低濃度のサブ領域PR1を高濃度のサブ領域PR2よりも転送トランジスタTXのゲート電極Gt(または、フローティングディフュージョンFD)に近い側に配置した。フォトダイオードPDが形成される領域の半導体基板SBの主面に、広範囲にわたって(特に、ゲート電極Gtの近くに)表面層(p型半導体層PR)を形成することができるので、暗電流および暗時白欠陥を低減できる。
本実施の形態2は、実施の形態1の変形例に相当する。本実施の形態2では、フォトダイオードPDの表面層がサブ領域PR1、PR2、PR3で構成されている。図25は、本実施の形態2の半導体装置の画素に含まれるフォトダイオードPDと転送トランジスタTXを示す平面図である。実施の形態1の場合と同様に、フォトダイオードPDのp型半導体領域である表面層を構成するサブ領域PR1、PR2、PR3を図示している。図26は、本実施の形態2の半導体装置の断面図であり、図25のA−A線に沿った断面図に対応している。
本実施の形態3は、実施の形態1の変形例に相当する。本実施の形態3では、フォトダイオードPDの表面層がサブ領域PR1、PR2、PR4で構成されている。図28は、本実施の形態3の半導体装置の画素に含まれるフォトダイオードPDと転送トランジスタTXを示す平面図である。実施の形態1の場合と同様に、フォトダイオードPDのp型半導体領域である表面層を構成するサブ領域PR1、PR2、PR4を図示している。図29は、本実施の形態3の半導体装置の断面図であり、図28のA−A線に沿った断面図に対応している。図30は、本実施の形態3の半導体装置の製造工程を示す断面図であり、図28のA−A線に沿った断面図に対応している。
本実施の形態4は、実施の形態1の変形例に相当する。本実施の形態4では、フォトダイオードPDの表面層がサブ領域PR1、PR2、PR5で構成されている。図31は、本実施の形態4の半導体装置の画素に含まれるフォトダイオードPDと転送トランジスタTXを示す平面図である。実施の形態1の場合と同様に、フォトダイオードPDのp型半導体領域である表面層を構成するサブ領域PR1、PR2、PR5を図示している。図32は、本実施の形態4の半導体装置の断面図であり、図31のC−C線に沿った断面図に対応している。
本実施の形態5は、実施の形態1の半導体装置の製造方法に関する変形例に相当する。実施の形態1では、図17を用いて説明したように、表面層であるp型半導体領域PRを構成するサブ領域PR1、PR2を異なるイオン注入工程を用いて形成した(図7のS6工程)。本実施の形態5では、表面層を構成するサブ領域PR6、PR7を一回のイオン注入工程で形成する。
Gt ゲート電極
NW n型半導体領域
PD フォトダイオード
PR p型半導体領域
PR1 第1サブ領域
PR2 第2サブ領域
TX 転送トランジスタ
Claims (8)
- 電荷蓄積層および前記電荷蓄積層の上に配置された表面層を有するフォトダイオードと、第1ゲート電極とフローティングディフュージョンを有し、前記電荷蓄積層の電荷を前記フローティングディフュージョンに転送する転送トランジスタと、を有する半導体装置の製造方法であって、
(a)半導体基板の主面に前記第1ゲート電極を形成する工程、
(b)前記第1ゲート電極の一端側に第1導電型の前記電荷蓄積層を形成する工程、
(c)前記電荷蓄積層内に、前記第1導電型とは反対導電型である第2導電型の表面層を形成する工程、
を有し、
前記工程(b)では、平面視において、前記電荷蓄積層の一部が前記第1ゲート電極と重なるように前記電荷蓄積層を形成し、
前記工程(c)は、
(c1)前記第1ゲート電極をマスクとして、前記半導体基板主面の法線に対して前記フローティングディフュージョン側に第1角度で傾斜した方向から、第2導電型の第1不純物を前記電荷蓄積層内にイオン注入して第1サブ領域を形成する工程、
(c2)前記第1ゲート電極をマスクに、前記半導体基板主面の法線に対して前記フローティングディフュージョン側に第2角度で傾斜した方向から、第2導電型の第2不純物を前記電荷蓄積層内にイオン注入して第2サブ領域を形成する工程、
を有し、
前記第1不純物の不純物濃度は、前記第2不純物の不純物濃度よりも低く、前記第1角度は前記第2角度よりも小である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1角度は10〜20°であり、前記第2角度は30°である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記工程(c)は、さらに、
(c3)前記第1ゲート電極をマスクに、前記半導体基板主面の法線に対して第3角度で、第2導電型の第3不純物を前記半導体基板にイオン注入して第3サブ領域を形成する工程、
を有し、
前記第3不純物の不純物濃度は、前記第1不純物の不純物濃度よりも低い、半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記第3角度は前記第1角度よりも小である、半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記第3角度は、前記法線に対して、前記第1角度と反対方向である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、さらに、
(d)前記第1ゲート電極を覆うように、前記半導体基板上に第1絶縁膜を堆積する工程、
(e)前記第1絶縁膜上に第2絶縁膜を堆積する工程、
(f)前記フォトダイオードの形成領域を覆い、前記フローティングディフュージョンの形成領域を露出する第1マスク層で前記半導体基板を覆った状態で、前記第2絶縁膜および前記第1絶縁膜に異方性ドライエッチングを施し、前記第1ゲート電極の他端側に第1側壁絶縁膜を形成する工程、
(g)前記第1ゲート電極および第1側壁絶縁膜に対して自己整合で、前記半導体基板主面に前記フローティングディフュージョンを形成する工程、
を有する、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記工程(a)は、前記半導体基板主面に、第2ゲート電極を形成する工程を含み、
前記工程(d)において、前記第1絶縁膜は、前記第2ゲート電極も覆うように形成され、
前記工程(d)と(e)の間に、
(h)前記第1ゲート電極を覆い、前記第2ゲート電極を露出する第2マスクで、前記半導体基板を覆った状態で、前記第1絶縁膜に異方性ドライエッチングを施し、前記第2ゲート電極の側壁にオフセットスペーサを形成する工程、
(i)前記第2ゲート電極および前記オフセットスペーサに対して自己整合で、前記半導体基板主面に前記第1導電型の第1半導体領域を形成する工程、
を有する、半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記工程(f)は、前記第2ゲート電極の側壁に、前記オフセットスペーサを介して第2側壁絶縁膜を形成する工程、
前記工程(g)は、前記第2ゲート電極および前記第2側壁絶縁膜に対して自己整合で、前記半導体基板主面に前記第1導電型の第2半導体領域を形成する工程、
を含む、半導体装置の製造方法。
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