JP6317550B2 - Emi対策回路 - Google Patents
Emi対策回路 Download PDFInfo
- Publication number
- JP6317550B2 JP6317550B2 JP2013139868A JP2013139868A JP6317550B2 JP 6317550 B2 JP6317550 B2 JP 6317550B2 JP 2013139868 A JP2013139868 A JP 2013139868A JP 2013139868 A JP2013139868 A JP 2013139868A JP 6317550 B2 JP6317550 B2 JP 6317550B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- clock signal
- timing
- circuit
- circuit block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000008859 change Effects 0.000 claims description 124
- 238000001514 detection method Methods 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 32
- 230000001360 synchronised effect Effects 0.000 claims description 23
- 230000004044 response Effects 0.000 claims description 14
- 230000000873 masking effect Effects 0.000 claims description 10
- 238000003708 edge detection Methods 0.000 description 35
- 230000000630 rising effect Effects 0.000 description 32
- 238000000034 method Methods 0.000 description 22
- 238000012545 processing Methods 0.000 description 22
- 230000003111 delayed effect Effects 0.000 description 21
- 230000008569 process Effects 0.000 description 19
- 230000006870 function Effects 0.000 description 13
- 230000000875 corresponding effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000007423 decrease Effects 0.000 description 9
- 230000010355 oscillation Effects 0.000 description 9
- 230000003247 decreasing effect Effects 0.000 description 8
- 230000005855 radiation Effects 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 238000003786 synthesis reaction Methods 0.000 description 5
- 230000010365 information processing Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 2
- 238000010130 dispersion processing Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 208000032365 Electromagnetic interference Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013139868A JP6317550B2 (ja) | 2013-07-03 | 2013-07-03 | Emi対策回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013139868A JP6317550B2 (ja) | 2013-07-03 | 2013-07-03 | Emi対策回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015015540A JP2015015540A (ja) | 2015-01-22 |
| JP2015015540A5 JP2015015540A5 (enExample) | 2016-05-19 |
| JP6317550B2 true JP6317550B2 (ja) | 2018-04-25 |
Family
ID=52436997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013139868A Active JP6317550B2 (ja) | 2013-07-03 | 2013-07-03 | Emi対策回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6317550B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6414497B2 (ja) * | 2015-03-25 | 2018-10-31 | アイシン・エィ・ダブリュ株式会社 | メモリコントローラ |
| JP7546559B2 (ja) * | 2018-10-24 | 2024-09-06 | マジック リープ, インコーポレイテッド | 非同期asic |
| JP7418159B2 (ja) | 2019-04-19 | 2024-01-19 | キヤノン株式会社 | 情報処理装置 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188516A (ja) * | 1986-02-14 | 1987-08-18 | Nec Corp | 遅延回路 |
| JPH10124168A (ja) * | 1996-10-18 | 1998-05-15 | Nkk Corp | 可変クロック動作システム |
| JP2002108493A (ja) * | 2000-09-29 | 2002-04-10 | Fujitsu General Ltd | クロック位相シフト回路 |
| US7706484B2 (en) * | 2006-06-22 | 2010-04-27 | International Business Machines Corporation | Coherent frequency clock generation and spectrum management with non-coherent phase |
| US8564336B2 (en) * | 2008-10-29 | 2013-10-22 | Nec Corporation | Clock frequency divider circuit and clock frequency division method |
-
2013
- 2013-07-03 JP JP2013139868A patent/JP6317550B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2015015540A (ja) | 2015-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6775342B1 (en) | Digital phase shifter | |
| JP4562787B2 (ja) | Pll回路 | |
| US6906562B1 (en) | Counter-based clock multiplier circuits and methods | |
| US8547154B2 (en) | Programmable duty cycle selection using incremental pulse widths | |
| US9742447B2 (en) | Clock signal generating apparatus, clock signal generating method, and medium | |
| JP6317550B2 (ja) | Emi対策回路 | |
| TW202318808A (zh) | Pll電路及發送系統 | |
| TWI495266B (zh) | 環型振盪器電路 | |
| KR102140117B1 (ko) | 클럭 위상 조절 회로 및 이를 포함하는 반도체 장치 | |
| US20150381191A1 (en) | Variable delay component ring oscillator with phase shifting select switch | |
| JPWO2008056551A1 (ja) | クロック信号分周回路 | |
| JP5928590B2 (ja) | クロック信号生成装置、クロック信号生成方法及びコンピュータ読取り可能記録媒体 | |
| KR101297413B1 (ko) | 적응형 클럭 생성 장치 및 방법 | |
| US7157953B1 (en) | Circuit for and method of employing a clock signal | |
| US20170163409A1 (en) | Phase synchronization circuit and phase synchronization method | |
| JP2004032586A (ja) | 逓倍pll回路 | |
| JP4371598B2 (ja) | 逓倍クロック発生回路 | |
| WO2002029975A2 (en) | Digital phase shifter | |
| JP4666670B2 (ja) | 通信装置及びその折り返し試験方法 | |
| JP2015015540A5 (enExample) | ||
| TWI469529B (zh) | 非整數頻率時脈產生電路及其方法 | |
| US7427886B2 (en) | Clock generating method and circuit thereof | |
| US7924966B2 (en) | Symmetry corrected high frequency digital divider | |
| JP6950172B2 (ja) | スペクトラム拡散クロック発生回路 | |
| JP2015222918A (ja) | フラクショナルpll回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160325 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160325 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161226 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170127 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170322 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171002 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20171120 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180323 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180330 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6317550 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |