JP6312818B2 - 拡散長保護された回路および設計方法 - Google Patents

拡散長保護された回路および設計方法 Download PDF

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Publication number
JP6312818B2
JP6312818B2 JP2016516800A JP2016516800A JP6312818B2 JP 6312818 B2 JP6312818 B2 JP 6312818B2 JP 2016516800 A JP2016516800 A JP 2016516800A JP 2016516800 A JP2016516800 A JP 2016516800A JP 6312818 B2 JP6312818 B2 JP 6312818B2
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JP
Japan
Prior art keywords
lod
protected
circuit
pulse
region
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Active
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JP2016516800A
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English (en)
Japanese (ja)
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JP2016526301A (ja
JP2016526301A5 (enExample
Inventor
ベルーア、カシャイアプ・ラマチャンドラ
チンターラパッリ・レッディー、ハリクリシュナ
サン−ローレン、マーチン
カマル、プラトゥシュ
パテル、プラヤグ・バーヌブハイ
タージオグル、イージン
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Qualcomm Inc
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Qualcomm Inc
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Publication of JP2016526301A publication Critical patent/JP2016526301A/ja
Publication of JP2016526301A5 publication Critical patent/JP2016526301A5/ja
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Publication of JP6312818B2 publication Critical patent/JP6312818B2/ja
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2016516800A 2013-05-29 2014-05-28 拡散長保護された回路および設計方法 Active JP6312818B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,052 2013-05-29
US13/905,052 US9093995B2 (en) 2013-05-29 2013-05-29 Length-of-diffusion protected circuit and method of design
PCT/US2014/039867 WO2014194007A2 (en) 2013-05-29 2014-05-28 Length-of-diffusion protected circuit and method of design

Publications (3)

Publication Number Publication Date
JP2016526301A JP2016526301A (ja) 2016-09-01
JP2016526301A5 JP2016526301A5 (enExample) 2017-06-22
JP6312818B2 true JP6312818B2 (ja) 2018-04-18

Family

ID=51022461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016516800A Active JP6312818B2 (ja) 2013-05-29 2014-05-28 拡散長保護された回路および設計方法

Country Status (7)

Country Link
US (1) US9093995B2 (enExample)
EP (1) EP3005183B1 (enExample)
JP (1) JP6312818B2 (enExample)
KR (1) KR20160013161A (enExample)
CN (1) CN105264531B (enExample)
BR (1) BR112015029871A2 (enExample)
WO (1) WO2014194007A2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10282503B2 (en) * 2016-06-25 2019-05-07 Qualcomm Incorporated Mitigating length-of-diffusion effect for logic cells and placement thereof
CN113204935B (zh) * 2021-05-08 2023-03-24 山东英信计算机技术有限公司 一种电源模块化设计方法及装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001285028A (ja) * 2000-03-29 2001-10-12 Fujitsu General Ltd 同期終端回路
WO2004038917A1 (ja) * 2002-10-25 2004-05-06 Renesas Technology Corp. 半導体集積回路
JP2006121443A (ja) * 2004-10-21 2006-05-11 Matsushita Electric Ind Co Ltd パルス生成装置
JP2006339948A (ja) * 2005-06-01 2006-12-14 Renesas Technology Corp パルスラッチ回路及び半導体集積回路
US7920403B2 (en) * 2005-07-27 2011-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. ROM cell array structure
US7484198B2 (en) 2006-02-27 2009-01-27 Synopsys, Inc. Managing integrated circuit stress using dummy diffusion regions
US7475381B2 (en) * 2006-03-30 2009-01-06 Intel Corporation Shallow trench avoidance in integrated circuits
JP2008118004A (ja) * 2006-11-07 2008-05-22 Nec Electronics Corp 半導体集積回路
US7958465B2 (en) 2008-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy pattern design for reducing device performance drift
US8232824B2 (en) 2009-04-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Clock circuit and method for pulsed latch circuits
WO2011043284A1 (ja) * 2009-10-06 2011-04-14 株式会社日立製作所 半導体集積回路装置
US8610236B2 (en) 2010-08-06 2013-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Edge devices layout for improved performance
WO2012120599A1 (ja) * 2011-03-04 2012-09-13 ルネサスエレクトロニクス株式会社 半導体装置
EP2509027B1 (en) * 2011-04-04 2019-02-06 Nxp B.V. Method for handling collision in an identification system
US20120256273A1 (en) 2011-04-08 2012-10-11 Yu-Ho Chiang Method of unifying device performance within die

Also Published As

Publication number Publication date
BR112015029871A2 (pt) 2017-07-25
CN105264531A (zh) 2016-01-20
KR20160013161A (ko) 2016-02-03
WO2014194007A3 (en) 2015-01-22
US20140354338A1 (en) 2014-12-04
CN105264531B (zh) 2019-04-19
JP2016526301A (ja) 2016-09-01
EP3005183B1 (en) 2020-07-29
EP3005183A2 (en) 2016-04-13
US9093995B2 (en) 2015-07-28
WO2014194007A2 (en) 2014-12-04

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