CN105264531B - 扩散长度受保护的电路和设计方法 - Google Patents

扩散长度受保护的电路和设计方法 Download PDF

Info

Publication number
CN105264531B
CN105264531B CN201480030890.9A CN201480030890A CN105264531B CN 105264531 B CN105264531 B CN 105264531B CN 201480030890 A CN201480030890 A CN 201480030890A CN 105264531 B CN105264531 B CN 105264531B
Authority
CN
China
Prior art keywords
lod
circuit
protected
transistors
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480030890.9A
Other languages
English (en)
Chinese (zh)
Other versions
CN105264531A (zh
Inventor
K·R·贝鲁尔
雷迪 H·琴恩塔拉帕利
M·圣-劳伦特
P·卡马尔
P·B·帕特尔
E·特泽格鲁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105264531A publication Critical patent/CN105264531A/zh
Application granted granted Critical
Publication of CN105264531B publication Critical patent/CN105264531B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
CN201480030890.9A 2013-05-29 2014-05-28 扩散长度受保护的电路和设计方法 Active CN105264531B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,052 2013-05-29
US13/905,052 US9093995B2 (en) 2013-05-29 2013-05-29 Length-of-diffusion protected circuit and method of design
PCT/US2014/039867 WO2014194007A2 (en) 2013-05-29 2014-05-28 Length-of-diffusion protected circuit and method of design

Publications (2)

Publication Number Publication Date
CN105264531A CN105264531A (zh) 2016-01-20
CN105264531B true CN105264531B (zh) 2019-04-19

Family

ID=51022461

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480030890.9A Active CN105264531B (zh) 2013-05-29 2014-05-28 扩散长度受保护的电路和设计方法

Country Status (7)

Country Link
US (1) US9093995B2 (enExample)
EP (1) EP3005183B1 (enExample)
JP (1) JP6312818B2 (enExample)
KR (1) KR20160013161A (enExample)
CN (1) CN105264531B (enExample)
BR (1) BR112015029871A2 (enExample)
WO (1) WO2014194007A2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10282503B2 (en) * 2016-06-25 2019-05-07 Qualcomm Incorporated Mitigating length-of-diffusion effect for logic cells and placement thereof
CN113204935B (zh) * 2021-05-08 2023-03-24 山东英信计算机技术有限公司 一种电源模块化设计方法及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071454A (zh) * 2006-03-30 2007-11-14 英特尔公司 集成电路中的浅沟槽的防止

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001285028A (ja) * 2000-03-29 2001-10-12 Fujitsu General Ltd 同期終端回路
WO2004038917A1 (ja) * 2002-10-25 2004-05-06 Renesas Technology Corp. 半導体集積回路
JP2006121443A (ja) * 2004-10-21 2006-05-11 Matsushita Electric Ind Co Ltd パルス生成装置
JP2006339948A (ja) * 2005-06-01 2006-12-14 Renesas Technology Corp パルスラッチ回路及び半導体集積回路
US7920403B2 (en) * 2005-07-27 2011-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. ROM cell array structure
US7484198B2 (en) 2006-02-27 2009-01-27 Synopsys, Inc. Managing integrated circuit stress using dummy diffusion regions
JP2008118004A (ja) * 2006-11-07 2008-05-22 Nec Electronics Corp 半導体集積回路
US7958465B2 (en) 2008-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy pattern design for reducing device performance drift
US8232824B2 (en) 2009-04-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Clock circuit and method for pulsed latch circuits
WO2011043284A1 (ja) * 2009-10-06 2011-04-14 株式会社日立製作所 半導体集積回路装置
US8610236B2 (en) 2010-08-06 2013-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Edge devices layout for improved performance
WO2012120599A1 (ja) * 2011-03-04 2012-09-13 ルネサスエレクトロニクス株式会社 半導体装置
EP2509027B1 (en) * 2011-04-04 2019-02-06 Nxp B.V. Method for handling collision in an identification system
US20120256273A1 (en) 2011-04-08 2012-10-11 Yu-Ho Chiang Method of unifying device performance within die

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071454A (zh) * 2006-03-30 2007-11-14 英特尔公司 集成电路中的浅沟槽的防止

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A 65-nm Pulsed Latch with a Single Clocked Transistor;Martin Saint-Laurent等;《international symposium on low power electronics and design》;20070827;全文 *
Stress-Aware Design Methodology;Victor Moroz等;《proceeding of 7th international symposium on quality electronic design》;20060327;全文 *

Also Published As

Publication number Publication date
BR112015029871A2 (pt) 2017-07-25
CN105264531A (zh) 2016-01-20
KR20160013161A (ko) 2016-02-03
JP6312818B2 (ja) 2018-04-18
WO2014194007A3 (en) 2015-01-22
US20140354338A1 (en) 2014-12-04
JP2016526301A (ja) 2016-09-01
EP3005183B1 (en) 2020-07-29
EP3005183A2 (en) 2016-04-13
US9093995B2 (en) 2015-07-28
WO2014194007A2 (en) 2014-12-04

Similar Documents

Publication Publication Date Title
JP6037570B2 (ja) 複数の電圧閾値を有するデバイスのための二重のポリラインパターニングを用いたスタンダードセルのアーキテクチャ
CN104969298B (zh) 用于对存储器单元进行编程的系统和方法
KR101252698B1 (ko) 클록 게이팅 시스템 및 방법
US20140327510A1 (en) Electronic device having asymmetrical through glass vias
WO2011109510A1 (en) System and method of test mode gate operation
CN105264531B (zh) 扩散长度受保护的电路和设计方法
CN104541330B (zh) 使用脉冲锁存器及阻挡门来执行扫描测试的系统和方法
US10515944B2 (en) Integrated circuit and method of generating integrated circuit layout
US9461040B2 (en) System and method of varying gate lengths of multiple cores
US11757405B2 (en) Oscillator circuit
CN114586280B (zh) 一种振荡器电路
CN109155286A (zh) 异构单元阵列
US20140068535A1 (en) System and method for configuring a transistor device using rx tuck
US12475292B2 (en) Circuit layout generation system
JP2009037482A (ja) シミュレーション方法及びプログラム
US20090140245A1 (en) Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process
US9542518B2 (en) User experience based management technique for mobile system-on-chips
US10778146B2 (en) Integrated circuit voltage-controlled oscillator with late-stage fabrication tuning
JP2004355438A (ja) 回路シミュレーション用入力ファイル生成システム及び生成方法
CN105045999A (zh) 一种mosvar的建模方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant