KR20160013161A - 확산-길이 보호된 회로 및 설계 방법 - Google Patents

확산-길이 보호된 회로 및 설계 방법 Download PDF

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Publication number
KR20160013161A
KR20160013161A KR1020157036436A KR20157036436A KR20160013161A KR 20160013161 A KR20160013161 A KR 20160013161A KR 1020157036436 A KR1020157036436 A KR 1020157036436A KR 20157036436 A KR20157036436 A KR 20157036436A KR 20160013161 A KR20160013161 A KR 20160013161A
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KR
South Korea
Prior art keywords
circuit
pulse
gap
transistors
circuit design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020157036436A
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English (en)
Korean (ko)
Inventor
카쉬야프 라마찬드라 벨루르
하리크리쉬나 친타라팔리 레디
마틴 세인트-로렌트
프라투쉬 카말
프라야그 바누바이 파텔
에신 터지오글루
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160013161A publication Critical patent/KR20160013161A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G06F17/5068—
    • G06F17/5081—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
KR1020157036436A 2013-05-29 2014-05-28 확산-길이 보호된 회로 및 설계 방법 Withdrawn KR20160013161A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,052 2013-05-29
US13/905,052 US9093995B2 (en) 2013-05-29 2013-05-29 Length-of-diffusion protected circuit and method of design
PCT/US2014/039867 WO2014194007A2 (en) 2013-05-29 2014-05-28 Length-of-diffusion protected circuit and method of design

Publications (1)

Publication Number Publication Date
KR20160013161A true KR20160013161A (ko) 2016-02-03

Family

ID=51022461

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157036436A Withdrawn KR20160013161A (ko) 2013-05-29 2014-05-28 확산-길이 보호된 회로 및 설계 방법

Country Status (7)

Country Link
US (1) US9093995B2 (enExample)
EP (1) EP3005183B1 (enExample)
JP (1) JP6312818B2 (enExample)
KR (1) KR20160013161A (enExample)
CN (1) CN105264531B (enExample)
BR (1) BR112015029871A2 (enExample)
WO (1) WO2014194007A2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10282503B2 (en) * 2016-06-25 2019-05-07 Qualcomm Incorporated Mitigating length-of-diffusion effect for logic cells and placement thereof
CN113204935B (zh) * 2021-05-08 2023-03-24 山东英信计算机技术有限公司 一种电源模块化设计方法及装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001285028A (ja) * 2000-03-29 2001-10-12 Fujitsu General Ltd 同期終端回路
WO2004038917A1 (ja) * 2002-10-25 2004-05-06 Renesas Technology Corp. 半導体集積回路
JP2006121443A (ja) * 2004-10-21 2006-05-11 Matsushita Electric Ind Co Ltd パルス生成装置
JP2006339948A (ja) * 2005-06-01 2006-12-14 Renesas Technology Corp パルスラッチ回路及び半導体集積回路
US7920403B2 (en) * 2005-07-27 2011-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. ROM cell array structure
US7484198B2 (en) 2006-02-27 2009-01-27 Synopsys, Inc. Managing integrated circuit stress using dummy diffusion regions
US7475381B2 (en) * 2006-03-30 2009-01-06 Intel Corporation Shallow trench avoidance in integrated circuits
JP2008118004A (ja) * 2006-11-07 2008-05-22 Nec Electronics Corp 半導体集積回路
US7958465B2 (en) 2008-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy pattern design for reducing device performance drift
US8232824B2 (en) 2009-04-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Clock circuit and method for pulsed latch circuits
WO2011043284A1 (ja) * 2009-10-06 2011-04-14 株式会社日立製作所 半導体集積回路装置
US8610236B2 (en) 2010-08-06 2013-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Edge devices layout for improved performance
WO2012120599A1 (ja) * 2011-03-04 2012-09-13 ルネサスエレクトロニクス株式会社 半導体装置
EP2509027B1 (en) * 2011-04-04 2019-02-06 Nxp B.V. Method for handling collision in an identification system
US20120256273A1 (en) 2011-04-08 2012-10-11 Yu-Ho Chiang Method of unifying device performance within die

Also Published As

Publication number Publication date
BR112015029871A2 (pt) 2017-07-25
CN105264531A (zh) 2016-01-20
JP6312818B2 (ja) 2018-04-18
WO2014194007A3 (en) 2015-01-22
US20140354338A1 (en) 2014-12-04
CN105264531B (zh) 2019-04-19
JP2016526301A (ja) 2016-09-01
EP3005183B1 (en) 2020-07-29
EP3005183A2 (en) 2016-04-13
US9093995B2 (en) 2015-07-28
WO2014194007A2 (en) 2014-12-04

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20151223

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid