BR112015029871A2 - circuito protegido por comprimento de difusão e método de disign - Google Patents

circuito protegido por comprimento de difusão e método de disign

Info

Publication number
BR112015029871A2
BR112015029871A2 BR112015029871A BR112015029871A BR112015029871A2 BR 112015029871 A2 BR112015029871 A2 BR 112015029871A2 BR 112015029871 A BR112015029871 A BR 112015029871A BR 112015029871 A BR112015029871 A BR 112015029871A BR 112015029871 A2 BR112015029871 A2 BR 112015029871A2
Authority
BR
Brazil
Prior art keywords
diffusion length
disign
circuit protected
circuit
pulsed
Prior art date
Application number
BR112015029871A
Other languages
English (en)
Portuguese (pt)
Inventor
Terzioglu Esin
Chintarlapalli Reddy Harikrishna
Ramachandra Bellur Kashyap
Saint-Laurent Martin
Kamal Pratyush
Bhanubhai Patel Prayag
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112015029871A2 publication Critical patent/BR112015029871A2/pt

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
BR112015029871A 2013-05-29 2014-05-28 circuito protegido por comprimento de difusão e método de disign BR112015029871A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/905,052 US9093995B2 (en) 2013-05-29 2013-05-29 Length-of-diffusion protected circuit and method of design
PCT/US2014/039867 WO2014194007A2 (en) 2013-05-29 2014-05-28 Length-of-diffusion protected circuit and method of design

Publications (1)

Publication Number Publication Date
BR112015029871A2 true BR112015029871A2 (pt) 2017-07-25

Family

ID=51022461

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015029871A BR112015029871A2 (pt) 2013-05-29 2014-05-28 circuito protegido por comprimento de difusão e método de disign

Country Status (7)

Country Link
US (1) US9093995B2 (enExample)
EP (1) EP3005183B1 (enExample)
JP (1) JP6312818B2 (enExample)
KR (1) KR20160013161A (enExample)
CN (1) CN105264531B (enExample)
BR (1) BR112015029871A2 (enExample)
WO (1) WO2014194007A2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10282503B2 (en) * 2016-06-25 2019-05-07 Qualcomm Incorporated Mitigating length-of-diffusion effect for logic cells and placement thereof
CN113204935B (zh) * 2021-05-08 2023-03-24 山东英信计算机技术有限公司 一种电源模块化设计方法及装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001285028A (ja) * 2000-03-29 2001-10-12 Fujitsu General Ltd 同期終端回路
WO2004038917A1 (ja) * 2002-10-25 2004-05-06 Renesas Technology Corp. 半導体集積回路
JP2006121443A (ja) * 2004-10-21 2006-05-11 Matsushita Electric Ind Co Ltd パルス生成装置
JP2006339948A (ja) * 2005-06-01 2006-12-14 Renesas Technology Corp パルスラッチ回路及び半導体集積回路
US7920403B2 (en) * 2005-07-27 2011-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. ROM cell array structure
US7484198B2 (en) 2006-02-27 2009-01-27 Synopsys, Inc. Managing integrated circuit stress using dummy diffusion regions
US7475381B2 (en) * 2006-03-30 2009-01-06 Intel Corporation Shallow trench avoidance in integrated circuits
JP2008118004A (ja) * 2006-11-07 2008-05-22 Nec Electronics Corp 半導体集積回路
US7958465B2 (en) 2008-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy pattern design for reducing device performance drift
US8232824B2 (en) 2009-04-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Clock circuit and method for pulsed latch circuits
US8772880B2 (en) * 2009-10-06 2014-07-08 Hitachi, Ltd. Semiconductor integrated circuit device
US8610236B2 (en) 2010-08-06 2013-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Edge devices layout for improved performance
WO2012120599A1 (ja) * 2011-03-04 2012-09-13 ルネサスエレクトロニクス株式会社 半導体装置
EP2509027B1 (en) * 2011-04-04 2019-02-06 Nxp B.V. Method for handling collision in an identification system
US20120256273A1 (en) 2011-04-08 2012-10-11 Yu-Ho Chiang Method of unifying device performance within die

Also Published As

Publication number Publication date
CN105264531B (zh) 2019-04-19
CN105264531A (zh) 2016-01-20
EP3005183B1 (en) 2020-07-29
US20140354338A1 (en) 2014-12-04
US9093995B2 (en) 2015-07-28
KR20160013161A (ko) 2016-02-03
EP3005183A2 (en) 2016-04-13
WO2014194007A2 (en) 2014-12-04
JP6312818B2 (ja) 2018-04-18
WO2014194007A3 (en) 2015-01-22
JP2016526301A (ja) 2016-09-01

Similar Documents

Publication Publication Date Title
MX2019009853A (es) Terapia de combinacion que incluye un inhibidor mdm2 y uno o mas agentes farmaceuticamente activos adicionales para el tratamiento de canceres.
MX2020004724A (es) Composiciones de inh-c1 y métodos para la prevención y el tratamiento de trastornos asociados con la deficiencia del inhibidor de c1 esterasa.
BR112015032445A2 (pt) componente semicondutor orgânico
MX2018007155A (es) Heteroarilhidroxipirimidinonas como agonistas del receptor de apelina (apj).
MX372669B (es) Un compuesto que modifica el empalme del gen de foxm1 para usarse en la profilaxis o tratamiento de cáncer.
UY36949A (es) 2,4-dihidroxi-nicotinamidas como agonistas de apj
BR112018009124A8 (pt) estrutura absorvente
EP3179870C0 (en) ANTIMICROBIAL COMPOUNDS AND COMPOSITIONS AND USES THEREOF
BR112018003178A2 (pt) absorvente feminino com braçadeiras de barreira
CO2018011105A2 (es) 6-hidroxi-4-oxo-1,4-dihidropirimidin-5-carboxamidas como agonistas del receptor de apelina (apj)
CR20140501A (es) Nuevos diazaespirocicloalcanos y azaespirocicloalcanos
CL2016000221A1 (es) Anticuerpos anti-fgfr2iiib afucosilados.
MX2016003486A (es) Inhibidores de glucosilceramida sintasa para el tratamiento de enfermedades.
CL2016000392A1 (es) Análogos de cortistatina para el tratamiento de enfermedades con componente inflamatorio y/o inmune
CL2015002116A1 (es) Administración de compuesto anti-activin-a a un sujeto
BR112015008117A2 (pt) benzamidas
BR112019003577A2 (pt) métodos de tratamento da semente e produtos resultantes
MX2018007390A (es) Composiciones que comprenden acido 15-hidroxi eicosapentaenoico (15-hepe) y metodos de uso del mismo.
BR112015023387A2 (pt) composições lipídicas de racecodotril
MX340928B (es) Derivados de oxazolina e isoxazolina como moduladores de canales de calcio de liberación activa (crac).
FR3013937B1 (fr) Circuit d'attaque avec une source lumineuse a base de semi-conducteurs, ainsi que procede de fonctionnement d'un circuit d'attaque
BR112017019845A2 (pt) novas composições antivirais para o tratamento da gripe
BR112014017048A2 (pt) emulsão orgânica compreendendo dha e epa
MX2018003903A (es) Compuesto biciclico y uso del mismo para inhibicion de suv39h2.
BR112015022940A2 (pt) composições líquidas de racecadotrila

Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements
B350 Update of information on the portal [chapter 15.35 patent gazette]