JP6274784B2 - 電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法 - Google Patents

電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法 Download PDF

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JP6274784B2
JP6274784B2 JP2013174778A JP2013174778A JP6274784B2 JP 6274784 B2 JP6274784 B2 JP 6274784B2 JP 2013174778 A JP2013174778 A JP 2013174778A JP 2013174778 A JP2013174778 A JP 2013174778A JP 6274784 B2 JP6274784 B2 JP 6274784B2
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electronic device
resin layer
resin
device package
sealing
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Japanese (ja)
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JP2015043378A (ja
Inventor
豊田　英志
英志 豊田
豪士 志賀
豪士 志賀
石坂　剛
剛 石坂
祐作 清水
祐作 清水
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Nitto Denko Corp
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Nitto Denko Corp
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Priority to JP2013174778A priority Critical patent/JP6274784B2/ja
Priority to CN201480046689.XA priority patent/CN105493270A/zh
Priority to PCT/JP2014/069223 priority patent/WO2015029642A1/ja
Priority to SG11201601421QA priority patent/SG11201601421QA/en
Priority to TW103129208A priority patent/TW201509659A/zh
Publication of JP2015043378A publication Critical patent/JP2015043378A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
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    • H01L2924/153—Connection portion
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
JP2013174778A 2013-08-26 2013-08-26 電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法 Active JP6274784B2 (ja)

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Application Number Priority Date Filing Date Title
JP2013174778A JP6274784B2 (ja) 2013-08-26 2013-08-26 電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法
CN201480046689.XA CN105493270A (zh) 2013-08-26 2014-07-18 电子设备密封用树脂片及电子设备封装体的制造方法
PCT/JP2014/069223 WO2015029642A1 (ja) 2013-08-26 2014-07-18 電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法
SG11201601421QA SG11201601421QA (en) 2013-08-26 2014-07-18 Resin sheet for sealing electronic device and method for manufacturing electronic device package
TW103129208A TW201509659A (zh) 2013-08-26 2014-08-25 電子裝置封裝用樹脂片材及電子裝置封裝之製造方法

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JP2013174778A JP6274784B2 (ja) 2013-08-26 2013-08-26 電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法

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JP2015043378A JP2015043378A (ja) 2015-03-05
JP6274784B2 true JP6274784B2 (ja) 2018-02-07

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CN (1) CN105493270A (zh)
SG (1) SG11201601421QA (zh)
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WO (1) WO2015029642A1 (zh)

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KR20160001169A (ko) * 2014-06-26 2016-01-06 삼성전자주식회사 마킹층을 포함하는 반도체 패키지
KR101685428B1 (ko) * 2015-07-20 2016-12-12 주식회사 이오테크닉스 레이저 마킹방법
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
JP7343989B2 (ja) * 2019-03-19 2023-09-13 日東電工株式会社 封止用シート
KR20220158705A (ko) 2020-03-26 2022-12-01 쇼와덴코머티리얼즈가부시끼가이샤 반도체 봉지용 이형 필름, 반도체 봉지용 마킹 필름, 반도체 패키지 및 반도체 패키지의 제조 방법
KR20220158704A (ko) 2020-03-26 2022-12-01 쇼와덴코머티리얼즈가부시끼가이샤 반도체 봉지용 마킹 필름, 반도체 봉지용 이형 필름, 반도체 패키지 및 반도체 패키지의 제조 방법
CN113992174A (zh) * 2021-11-03 2022-01-28 北京超材信息科技有限公司 声学装置封装结构
CN114024520B (zh) * 2021-11-03 2023-02-10 北京超材信息科技有限公司 声学装置双层覆膜工艺

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US5560845A (en) * 1994-02-28 1996-10-01 E. I. Du Pont De Nemours And Company Laser marking of fluoropolymer composition
JPH0873621A (ja) * 1994-09-07 1996-03-19 Toshiba Corp 樹脂シート
JP4682796B2 (ja) * 2005-04-19 2011-05-11 日立化成工業株式会社 封止用シート
JP2009141020A (ja) * 2007-12-04 2009-06-25 Furukawa Electric Co Ltd:The 電子部品封止用シート
JP5456642B2 (ja) * 2009-12-24 2014-04-02 日東電工株式会社 フリップチップ型半導体裏面用フィルム
JP5587220B2 (ja) * 2010-01-29 2014-09-10 日東電工株式会社 熱伝導性接着シート

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JP2015043378A (ja) 2015-03-05
SG11201601421QA (en) 2016-03-30
CN105493270A (zh) 2016-04-13
WO2015029642A1 (ja) 2015-03-05

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