JP6216157B2 - 電子部品装置及びその製造方法 - Google Patents

電子部品装置及びその製造方法 Download PDF

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Publication number
JP6216157B2
JP6216157B2 JP2013110634A JP2013110634A JP6216157B2 JP 6216157 B2 JP6216157 B2 JP 6216157B2 JP 2013110634 A JP2013110634 A JP 2013110634A JP 2013110634 A JP2013110634 A JP 2013110634A JP 6216157 B2 JP6216157 B2 JP 6216157B2
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Prior art keywords
electronic component
hole
connection pad
insulating layer
connection
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Japanese (ja)
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JP2014229855A5 (enExample
JP2014229855A (ja
Inventor
堀内 道夫
道夫 堀内
亮 深澤
亮 深澤
勇一 松田
勇一 松田
徳武 安衛
安衛 徳武
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2013110634A priority Critical patent/JP6216157B2/ja
Priority to US14/260,588 priority patent/US9373587B2/en
Publication of JP2014229855A publication Critical patent/JP2014229855A/ja
Publication of JP2014229855A5 publication Critical patent/JP2014229855A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2013110634A 2013-05-27 2013-05-27 電子部品装置及びその製造方法 Active JP6216157B2 (ja)

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JP2013110634A JP6216157B2 (ja) 2013-05-27 2013-05-27 電子部品装置及びその製造方法
US14/260,588 US9373587B2 (en) 2013-05-27 2014-04-24 Stacked electronic device

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JP2014229855A JP2014229855A (ja) 2014-12-08
JP2014229855A5 JP2014229855A5 (enExample) 2016-01-28
JP6216157B2 true JP6216157B2 (ja) 2017-10-18

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US9999136B2 (en) * 2014-12-15 2018-06-12 Ge Embedded Electronics Oy Method for fabrication of an electronic module and electronic module
JP7574747B2 (ja) * 2021-06-04 2024-10-29 株式会社デンソー 半導体装置およびその製造方法

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JPH06268101A (ja) * 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
JP2944449B2 (ja) 1995-02-24 1999-09-06 日本電気株式会社 半導体パッケージとその製造方法
US6180881B1 (en) * 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
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