JP6117790B2 - 配線基板、それを備えた実装構造体 - Google Patents
配線基板、それを備えた実装構造体 Download PDFInfo
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- JP6117790B2 JP6117790B2 JP2014528102A JP2014528102A JP6117790B2 JP 6117790 B2 JP6117790 B2 JP 6117790B2 JP 2014528102 A JP2014528102 A JP 2014528102A JP 2014528102 A JP2014528102 A JP 2014528102A JP 6117790 B2 JP6117790 B2 JP 6117790B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0263—Details about a collection of particles
- H05K2201/0269—Non-uniform distribution or concentration of particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/029—Woven fibrous reinforcement or textile
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
(実装構造体)
以下に、本発明の第1実施形態における配線基板を備えた実装構造体を、図面を参照しつつ詳細に説明する。
配線基板3は、電子部品2を支持するとともに、電子部品2を駆動もしくは制御するための電源や信号を電子部品2へ供給する機能を有する。この配線基板3は、コア基板5と、コア基板5の両主面に形成された一対のビルドアップ層6とを含んでいる。
コア基板5は、基体7と、基体7の両主面に形成された一対の導電層8と、基体7を貫通して一対の導電層8同士を電気的に接続した円筒状のスルーホール導体9と、スルーホール導体9の内部に充填された絶縁体10とを含んでいる。
ビルドアップ層6は、複数の導電層8と複数の第1樹脂層14と複数のビア導体15とを含んでいる。導電層8と第1樹脂層14とは交互に積層されている。第1樹脂層14を貫通したビア導体15によって、厚み方向に離れた導電層8同士が電気的に接続されている。
1樹脂層14における他の構成は、基体7と同様である。なお、第1樹脂層14の第1層領域R1の厚みは、基体7と同様に測定される。
次に、前述した実装構造体1の製造方法を、図4から図13を参照しつつ説明する。
(実装構造体)
次に、本発明の第2実施形態における配線基板を備えた実装構造体を、図面を参照しつつ詳細に説明する。なお、前述した第1実施形態と同様の構成に関しては説明を省略する。
次に、前述した第2実施形態の実装構造体1の製造方法を説明する。なお、前述した第1実施形態と同様の方法に関しては説明を省略する。
2 電子部品
3 配線基板
4 バンプ
5 コア基板
6 ビルドアップ層
7 基体
7x 基体前駆体
7y 樹脂基体層
8 導電層
9 スルーホール導体
10 絶縁体
11 第1樹脂部
11x 未硬化の第1樹脂
12 基材
13 無機絶縁粒子
13A 第1無機絶縁粒子
13B 第2無機絶縁粒子
14 第1樹脂層
14x 第1樹脂層前駆体
15 ビア導体
16 溶剤
17 ゾル
18 支持シート
19 粉末層
20 積層体
21 混合物
22 積層シート
23 第2樹脂層
23x 第2樹脂層前駆体
24 第2樹脂部
24x 未硬化の第2樹脂
25 第3無機絶縁粒子
G 空隙
R1 第1層領域
R2 第2層領域
S 境界面
Claims (5)
- 第1導電層と、1つの樹脂部および該樹脂部に分散した複数の無機絶縁粒子を有する、前記第1導電層を覆った第1樹脂層とを備え、
該第1樹脂層は、前記第1導電層の一主面および側面に接して該第1導電層を被覆する第1層領域と、該第1層領域の前記第1導電層とは反対側に位置し、前記第1層領域に配された第2層領域とを具備しており、
前記複数の無機絶縁粒子は、前記第1層領域に配された複数の第1無機絶縁粒子と、前記第2層領域に配された複数の第2無機絶縁粒子とを含んでおり、
前記第1層領域における前記第1無機絶縁粒子の含有割合は、前記第2層領域における前記第2無機絶縁粒子の含有割合よりも小さく、
前記第1層領域における前記第1無機絶縁粒子の含有割合は、前記第2層領域側から前記第1導電層側に向かって小さくなっていることを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記複数の第2無機絶縁粒子の平均粒子径は、前記複数の第1無機絶縁粒子の平均粒子径よりも大きいことを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記複数の第2無機絶縁粒子の粒子径における標準偏差は、前記複数の第1無機絶縁粒子の粒子径における標準偏差よりも大きいことを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記第1樹脂層の前記第2層領域側の一主面に配されているとともに該第1樹脂層よりもヤング率が小さい第2樹脂層と、該第2樹脂層の前記第1樹脂層とは反対側の主面に配された第2導電層とをさらに備えることを特徴とする配線基板。 - 請求項1に記載の配線基板と、該配線基板の一主面に実装された電子部品とを備えた実装構造体。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012171186 | 2012-08-01 | ||
JP2012171186 | 2012-08-01 | ||
JP2012198256 | 2012-09-10 | ||
JP2012198256 | 2012-09-10 | ||
PCT/JP2013/070173 WO2014021186A1 (ja) | 2012-08-01 | 2013-07-25 | 配線基板、それを備えた実装構造体および配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2014021186A1 JPWO2014021186A1 (ja) | 2016-07-21 |
JP6117790B2 true JP6117790B2 (ja) | 2017-04-19 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2014528102A Active JP6117790B2 (ja) | 2012-08-01 | 2013-07-25 | 配線基板、それを備えた実装構造体 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9814136B2 (ja) |
JP (1) | JP6117790B2 (ja) |
WO (1) | WO2014021186A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160242283A1 (en) * | 2013-10-29 | 2016-08-18 | Kyocera Corporation | Wiring board, and mounting structure and laminated sheet using the same |
WO2016143688A1 (ja) * | 2015-03-06 | 2016-09-15 | 京セラ株式会社 | 巻回体および基板用シート |
JP6711245B2 (ja) * | 2016-11-21 | 2020-06-17 | 株式会社デンソー | プリント基板の製造方法および電子装置の製造方法 |
CN109905957B (zh) * | 2017-12-11 | 2021-04-23 | 欣兴电子股份有限公司 | 电路板及其制造方法 |
TWI642335B (zh) * | 2017-12-11 | 2018-11-21 | 欣興電子股份有限公司 | 電路板及其製造方法 |
CN209643071U (zh) * | 2018-11-21 | 2019-11-15 | 奥特斯(中国)有限公司 | 一种部件载体 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2756075B2 (ja) * | 1993-08-06 | 1998-05-25 | 三菱電機株式会社 | 金属ベース基板およびそれを用いた電子機器 |
JP4895448B2 (ja) * | 2001-09-27 | 2012-03-14 | 京セラ株式会社 | 多層配線基板 |
JP4426805B2 (ja) * | 2002-11-11 | 2010-03-03 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
JP2004250674A (ja) | 2003-01-31 | 2004-09-09 | Sumitomo Chem Co Ltd | 樹脂フィルムおよびそれを用いた多層プリント配線板 |
TW200417295A (en) | 2003-01-31 | 2004-09-01 | Sumitomo Chemical Co | Resin film and multilayer printed wiring board using thereof |
JP2007180105A (ja) * | 2005-12-27 | 2007-07-12 | Sanyo Electric Co Ltd | 回路基板、回路基板を用いた回路装置、及び回路基板の製造方法 |
US8446734B2 (en) * | 2006-03-30 | 2013-05-21 | Kyocera Corporation | Circuit board and mounting structure |
US7745264B2 (en) * | 2007-09-04 | 2010-06-29 | Advanced Micro Devices, Inc. | Semiconductor chip with stratified underfill |
JP5121574B2 (ja) * | 2008-05-28 | 2013-01-16 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
JP2011029488A (ja) * | 2009-07-28 | 2011-02-10 | Kyocera Corp | 配線基板 |
JP2011187473A (ja) | 2010-03-04 | 2011-09-22 | Nec Corp | 半導体素子内蔵配線基板 |
KR101456088B1 (ko) | 2010-07-30 | 2014-11-03 | 쿄세라 코포레이션 | 절연 시트, 그 제조방법 및 그 절연 시트를 사용한 구조체의 제조방법 |
-
2013
- 2013-07-25 WO PCT/JP2013/070173 patent/WO2014021186A1/ja active Application Filing
- 2013-07-25 US US14/417,592 patent/US9814136B2/en active Active
- 2013-07-25 JP JP2014528102A patent/JP6117790B2/ja active Active
Also Published As
Publication number | Publication date |
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WO2014021186A1 (ja) | 2014-02-06 |
US20150305154A1 (en) | 2015-10-22 |
JPWO2014021186A1 (ja) | 2016-07-21 |
US9814136B2 (en) | 2017-11-07 |
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